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[Author] Jeong Beom KIM(3hit)

1-3hit
  • Novel Built-In Current Sensor for On-Line Current Testing

    Chul Ho KWAK  Jeong Beom KIM  

     
    LETTER-Integrated Electronics

      Vol:
    E86-C No:9
      Page(s):
    1898-1902

    This paper proposes a novel CMOS built-in current sensor (BICS) for on-line current testing. Proposed BICS detects abnormal current in circuit under test (CUT) and makes a Pass/Fail signal through comparison between the CUT current and the duplicated inverter current. This circuit consists of two current-to-voltage conversion transistors, a full swing generator, a voltage comparator, and an inverter block. It requires 16 transistors. Since this BICS does not require the extra clock, the added extra pin is only one output pin. Furthermore, the BICS does not require test mode selection. Therefore the BICS can be applied to on-line current testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When the CUT is an 8 8 parallel multiplier, the area overhead of the BICS is about 4.34%.

  • A CMOS Built-In Current Sensor for IDDQ Testing

    Jeong Beom KIM  Seung Ho HONG  

     
    LETTER-Integrated Electronics

      Vol:
    E89-C No:6
      Page(s):
    868-870

    This paper presents a new built-in current sensor (BICS) that detects defects using the current testing technique in CMOS integrated circuits. The proposed circuit is a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applicable in deep sub-micron process. The area overhead of the BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 µm standard CMOS technology.

  • 11-Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic

    Sun Hong AHN  Jeong Beom KIM  

     
    PAPER-Integrated Electronics

      Vol:
    E90-C No:3
      Page(s):
    623-627

    This paper describes an 11-Gb/s CMOS demultiplexer (DEMUX) using redundant multi-valued logic (RMVL). The proposed circuit is received to serial binary data and is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented DEMUX consists of eight integrators. The DEMUX is designed with 0.35 µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The DEMUX is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43 mW. This circuit is expected to operate at higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.

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