11-Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic

Sun Hong AHN; Jeong Beom KIM

doi:10.1093/ietele/e90-c.3.623

11-Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic

Sun Hong AHN, Jeong Beom KIM

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This paper describes an 11-Gb/s CMOS demultiplexer (DEMUX) using redundant multi-valued logic (RMVL). The proposed circuit is received to serial binary data and is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented DEMUX consists of eight integrators. The DEMUX is designed with 0.35 µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The DEMUX is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43 mW. This circuit is expected to operate at higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.3 pp.623-627

Publication Date: 2007/03/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.3.623

Type of Manuscript: PAPER

Category: Integrated Electronics

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Sun Hong AHN, Jeong Beom KIM, "11-Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 3, pp. 623-627, March 2007, doi: 10.1093/ietele/e90-c.3.623.
Abstract: This paper describes an 11-Gb/s CMOS demultiplexer (DEMUX) using redundant multi-valued logic (RMVL). The proposed circuit is received to serial binary data and is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented DEMUX consists of eight integrators. The DEMUX is designed with 0.35 µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The DEMUX is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43 mW. This circuit is expected to operate at higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.3.623/_p

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@ARTICLE{e90-c_3_623,
author={Sun Hong AHN, Jeong Beom KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={11-Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic},
year={2007},
volume={E90-C},
number={3},
pages={623-627},
abstract={This paper describes an 11-Gb/s CMOS demultiplexer (DEMUX) using redundant multi-valued logic (RMVL). The proposed circuit is received to serial binary data and is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented DEMUX consists of eight integrators. The DEMUX is designed with 0.35 µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The DEMUX is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43 mW. This circuit is expected to operate at higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.},
keywords={},
doi={10.1093/ietele/e90-c.3.623},
ISSN={1745-1353},
month={March},}

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TY - JOUR
TI - 11-Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic
T2 - IEICE TRANSACTIONS on Electronics
SP - 623
EP - 627
AU - Sun Hong AHN
AU - Jeong Beom KIM
PY - 2007
DO - 10.1093/ietele/e90-c.3.623
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2007
AB - This paper describes an 11-Gb/s CMOS demultiplexer (DEMUX) using redundant multi-valued logic (RMVL). The proposed circuit is received to serial binary data and is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented DEMUX consists of eight integrators. The DEMUX is designed with 0.35 µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The DEMUX is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43 mW. This circuit is expected to operate at higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.
ER -