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[Author] Ji-Hun EO(2hit)

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  • A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface

    Ji-Hun EO  Sang-Hun KIM  Young-Chan JANG  

     
    BRIEF PAPER-Electronic Circuits

      Vol:
    E94-C No:11
      Page(s):
    1798-1801

    A 200 kS/s 10-bit successive approximation (SA) analog-to-digital converter (ADC) with a rail-to-rail input signal is proposed for acquiring biosignals such as EEG and MEG signals. A split-capacitor-based digital-to-analog converter (SC-DAC) is used to reduce the power consumption and chip area. The SC-DAC's linearity is improved by using dummy capacitors and a small bootstrapped analog switch with a constant on-resistance, without increasing its area. A time-domain comparator with a replica circuit for clock feed-through noise compensation is designed by using a highly differential digital architecture involving a small area. Its area is about 50% less than that of a conventional time-domain comparator. The proposed SA ADC is implemented by using a 0.18-µm 1-poly 6-metal CMOS process with a 1 V supply. The measured DNL and INL are +0.44/-0.4 LSB and +0.71/-0.62 LSB, respectively. The SNDR is 55.43 dB for a 99.01 kHz analog input signal at a sampling rate of 200 kS/s. The power consumption and core area are 5 µW and 0.126 mm2, respectively. The FoM is 47 fJ/conversion-step.

  • An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 88 Point EEG/MEG Acquisition System

    Ji-Hun EO  Yeon-Ho JEONG  Young-Chan JANG  

     
    PAPER

      Vol:
    E96-A No:2
      Page(s):
    453-458

    An 8-bit 100-kS/s successive approximation (SA) analog-to-digital converter (ADC) is proposed for measuring EEG and MEG signals in an 88 point. The architectures of a SA ADC with a single-ended analog input and a split-capacitor-based digital-to-analog converter (SC-DAC) are used to reduce the power consumption and chip area of the entire ADC. The proposed SA ADC uses a time-domain comparator that has an input offset self-calibration circuit. It also includes a serial output interface to support a daisy channel that reduces the number of channels for the multi-point sensor interface. It is designed by using a 0.35-µm 1-poly 6-metal CMOS process with a 3.3 V supply to implement together with a conventional analog circuit such as a low-noise-amplifier. The measured DNL and INL of the SA ADC are +0.63/-0.46 and +0.46/-0.51 LSB, respectively. The SNDR is 48.39 dB for a 1.11 kHz analog input signal at a sampling rate of 100 kS/s. The power consumption and core area are 38.71 µW and 0.059 mm2, respectively.

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