An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 8<cd0215f.gif>8 Point EEG/MEG Acquisition System

Ji-Hun EO; Yeon-Ho JEONG; Young-Chan JANG

doi:10.1587/transfun.E96.A.453

An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 88 Point EEG/MEG Acquisition System

Ji-Hun EO, Yeon-Ho JEONG, Young-Chan JANG

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An 8-bit 100-kS/s successive approximation (SA) analog-to-digital converter (ADC) is proposed for measuring EEG and MEG signals in an 88 point. The architectures of a SA ADC with a single-ended analog input and a split-capacitor-based digital-to-analog converter (SC-DAC) are used to reduce the power consumption and chip area of the entire ADC. The proposed SA ADC uses a time-domain comparator that has an input offset self-calibration circuit. It also includes a serial output interface to support a daisy channel that reduces the number of channels for the multi-point sensor interface. It is designed by using a 0.35-µm 1-poly 6-metal CMOS process with a 3.3 V supply to implement together with a conventional analog circuit such as a low-noise-amplifier. The measured DNL and INL of the SA ADC are +0.63/-0.46 and +0.46/-0.51 LSB, respectively. The SNDR is 48.39 dB for a 1.11 kHz analog input signal at a sampling rate of 100 kS/s. The power consumption and core area are 38.71 µW and 0.059 mm², respectively.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.2 pp.453-458

Publication Date: 2013/02/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E96.A.453

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)

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Ji-Hun EO, Yeon-Ho JEONG, Young-Chan JANG, "An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 88 Point EEG/MEG Acquisition System" in IEICE TRANSACTIONS on Fundamentals, vol. E96-A, no. 2, pp. 453-458, February 2013, doi: 10.1587/transfun.E96.A.453.
Abstract: An 8-bit 100-kS/s successive approximation (SA) analog-to-digital converter (ADC) is proposed for measuring EEG and MEG signals in an 88 point. The architectures of a SA ADC with a single-ended analog input and a split-capacitor-based digital-to-analog converter (SC-DAC) are used to reduce the power consumption and chip area of the entire ADC. The proposed SA ADC uses a time-domain comparator that has an input offset self-calibration circuit. It also includes a serial output interface to support a daisy channel that reduces the number of channels for the multi-point sensor interface. It is designed by using a 0.35-µm 1-poly 6-metal CMOS process with a 3.3 V supply to implement together with a conventional analog circuit such as a low-noise-amplifier. The measured DNL and INL of the SA ADC are +0.63/-0.46 and +0.46/-0.51 LSB, respectively. The SNDR is 48.39 dB for a 1.11 kHz analog input signal at a sampling rate of 100 kS/s. The power consumption and core area are 38.71 µW and 0.059 mm², respectively.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.453/_p

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@ARTICLE{e96-a_2_453,
author={Ji-Hun EO, Yeon-Ho JEONG, Young-Chan JANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 88 Point EEG/MEG Acquisition System},
year={2013},
volume={E96-A},
number={2},
pages={453-458},
abstract={An 8-bit 100-kS/s successive approximation (SA) analog-to-digital converter (ADC) is proposed for measuring EEG and MEG signals in an 88 point. The architectures of a SA ADC with a single-ended analog input and a split-capacitor-based digital-to-analog converter (SC-DAC) are used to reduce the power consumption and chip area of the entire ADC. The proposed SA ADC uses a time-domain comparator that has an input offset self-calibration circuit. It also includes a serial output interface to support a daisy channel that reduces the number of channels for the multi-point sensor interface. It is designed by using a 0.35-µm 1-poly 6-metal CMOS process with a 3.3 V supply to implement together with a conventional analog circuit such as a low-noise-amplifier. The measured DNL and INL of the SA ADC are +0.63/-0.46 and +0.46/-0.51 LSB, respectively. The SNDR is 48.39 dB for a 1.11 kHz analog input signal at a sampling rate of 100 kS/s. The power consumption and core area are 38.71 µW and 0.059 mm², respectively.},
keywords={},
doi={10.1587/transfun.E96.A.453},
ISSN={1745-1337},
month={February},}

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TY - JOUR
TI - An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 88 Point EEG/MEG Acquisition System
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 453
EP - 458
AU - Ji-Hun EO
AU - Yeon-Ho JEONG
AU - Young-Chan JANG
PY - 2013
DO - 10.1587/transfun.E96.A.453
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2013
AB - An 8-bit 100-kS/s successive approximation (SA) analog-to-digital converter (ADC) is proposed for measuring EEG and MEG signals in an 88 point. The architectures of a SA ADC with a single-ended analog input and a split-capacitor-based digital-to-analog converter (SC-DAC) are used to reduce the power consumption and chip area of the entire ADC. The proposed SA ADC uses a time-domain comparator that has an input offset self-calibration circuit. It also includes a serial output interface to support a daisy channel that reduces the number of channels for the multi-point sensor interface. It is designed by using a 0.35-µm 1-poly 6-metal CMOS process with a 3.3 V supply to implement together with a conventional analog circuit such as a low-noise-amplifier. The measured DNL and INL of the SA ADC are +0.63/-0.46 and +0.46/-0.51 LSB, respectively. The SNDR is 48.39 dB for a 1.11 kHz analog input signal at a sampling rate of 100 kS/s. The power consumption and core area are 38.71 µW and 0.059 mm², respectively.
ER -