A new, simple test circuit for measuring the threshold voltage distribution of flash EEPROM cell transistors is described. This circuit makes it possible to perform a reliability test for a large number of memory cell transistors with easy static operation because it reduces the measuring time drastically. In addition, this circuit can measure the highest and lowest thresh-old voltages of memory cell transistors easily. This method is suitable for performing the reliability test, such as program/erase endurance test and data retention test, for a large number of flash memory cell transistors. The usefulness of this new test circuit has been confirmed by applying it to 64 Kbit NAND-type flash memory cell array.

In this paper we deal with Voronoi diagram in simply connected complete manifold with non positive curvature, called Hadamard manifold. We prove that a part of the Voronoi diagram can be characterized by hyperbolic Voronoi diagram. Voronoi diagram in simply connected complete manifold is also characterized for a given set of points satisfying a distance condition.

The routings in an analog PCB (printed circuit board) mainly consist of non-rectilinear and curved lines, which significantly affect the characteristics of an electric circuit. So, a building automatic design system for an analog PCB is still regarded as a difficult problem. In this paper, a new method for modelization of PCBs is proposed, replacing the wiring and the boundary on a PCB with surface charges, and a new routing searching method satisfying the condition of minimization of the total potential energy in all regions of a PCB. Also the applicability to an analog PCB wiring design is shown. From the basic study using computer simulation, it is found that a routing searched by this method is quite similar to the Steiner tree. In the end, it is shown that this routing can be searched by the steepest descent technique.