A new, simple test circuit for measuring the threshold voltage distribution of flash EEPROM cell transistors is described. This circuit makes it possible to perform a reliability test for a large number of memory cell transistors with easy static operation because it reduces the measuring time drastically. In addition, this circuit can measure the highest and lowest thresh-old voltages of memory cell transistors easily. This method is suitable for performing the reliability test, such as program/erase endurance test and data retention test, for a large number of flash memory cell transistors. The usefulness of this new test circuit has been confirmed by applying it to 64 Kbit NAND-type flash memory cell array.
Toshihiko HIMENO
Naohiro MATSUKAWA
Hiroaki HAZAMA
Koji SAKUI
Masamitsu OSHIKIRI
Kazunori MASUDA
Kazushige KANDA
Yasuo ITOH
Jin-ichi
MIYAMOTO
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Toshihiko HIMENO, Naohiro MATSUKAWA, Hiroaki HAZAMA, Koji SAKUI, Masamitsu OSHIKIRI, Kazunori MASUDA, Kazushige KANDA, Yasuo ITOH, Jin-ichi, MIYAMOTO, "A Novel Threshold Voltage Distribution Measuring Technique for Flash EEPROM Devices" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 2, pp. 145-151, February 1996, doi: .
Abstract: A new, simple test circuit for measuring the threshold voltage distribution of flash EEPROM cell transistors is described. This circuit makes it possible to perform a reliability test for a large number of memory cell transistors with easy static operation because it reduces the measuring time drastically. In addition, this circuit can measure the highest and lowest thresh-old voltages of memory cell transistors easily. This method is suitable for performing the reliability test, such as program/erase endurance test and data retention test, for a large number of flash memory cell transistors. The usefulness of this new test circuit has been confirmed by applying it to 64 Kbit NAND-type flash memory cell array.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e79-c_2_145/_p
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@ARTICLE{e79-c_2_145,
author={Toshihiko HIMENO, Naohiro MATSUKAWA, Hiroaki HAZAMA, Koji SAKUI, Masamitsu OSHIKIRI, Kazunori MASUDA, Kazushige KANDA, Yasuo ITOH, Jin-ichi, MIYAMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Novel Threshold Voltage Distribution Measuring Technique for Flash EEPROM Devices},
year={1996},
volume={E79-C},
number={2},
pages={145-151},
abstract={A new, simple test circuit for measuring the threshold voltage distribution of flash EEPROM cell transistors is described. This circuit makes it possible to perform a reliability test for a large number of memory cell transistors with easy static operation because it reduces the measuring time drastically. In addition, this circuit can measure the highest and lowest thresh-old voltages of memory cell transistors easily. This method is suitable for performing the reliability test, such as program/erase endurance test and data retention test, for a large number of flash memory cell transistors. The usefulness of this new test circuit has been confirmed by applying it to 64 Kbit NAND-type flash memory cell array.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A Novel Threshold Voltage Distribution Measuring Technique for Flash EEPROM Devices
T2 - IEICE TRANSACTIONS on Electronics
SP - 145
EP - 151
AU - Toshihiko HIMENO
AU - Naohiro MATSUKAWA
AU - Hiroaki HAZAMA
AU - Koji SAKUI
AU - Masamitsu OSHIKIRI
AU - Kazunori MASUDA
AU - Kazushige KANDA
AU - Yasuo ITOH
AU - Jin-ichi
AU - MIYAMOTO
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 1996
AB - A new, simple test circuit for measuring the threshold voltage distribution of flash EEPROM cell transistors is described. This circuit makes it possible to perform a reliability test for a large number of memory cell transistors with easy static operation because it reduces the measuring time drastically. In addition, this circuit can measure the highest and lowest thresh-old voltages of memory cell transistors easily. This method is suitable for performing the reliability test, such as program/erase endurance test and data retention test, for a large number of flash memory cell transistors. The usefulness of this new test circuit has been confirmed by applying it to 64 Kbit NAND-type flash memory cell array.
ER -