Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.

In this paper, a smart dressing system was implemented based on flexible pH sensors that can monitor the infection of a wounded area by tracking the pH value of the area. Motivated by the fabrication process widely used for semiconductors, the flexible pH sensor fabrication process was devised with a polyester (PET) film and a Si wafer, which deposits Au and Ag on a PET film. Because the electrodes are comprised of a working electrode and a reference electrode, the reference electrode was fabricated by synthesizing the Polyaniline (PANI) on Ag/AgCl, while the pH sensor has four channels to evenly measure the pH value in a wide area. The smart dressing system was constructed with four pH sensors, a single temperature sensor, a level shifter, a regulator, an analog-to-digital converter (ADC), and a monitoring PC. The measurement results show that our smart dressing system has a size of 5×5cm2 and can monitor the pH value range found in [3,9] with a sensitivity slope of 50mV/pH.

In this paper, characteristics of the 2-bit recessed channel memory with lifted-charge trapping nodes are investigated. The length between the charge trapping nodes through channel, which is defined as the effective memory node length (Meff), is extended by lifting up them. The dependence of VTH window and short channel effect (SCE) on the recessed depth is analyzed. Improvement of short channel effect is achieved because the recessed channel structure increases the effective channel length (Leff). Moreover, this device shows highly scalable memory characteristics without suffering from the bottom-side effect (BSE).

Real-time monitoring of heart rate (HR) and body temperature (BT) is crucial for the prognosis and the diagnosis of cardiovascular disease and healthcare. Since current monitoring systems are too rigid and bulky, it is not easy to attach them to the human body. Also, their large current consumption limits the working time. In this paper, we develop a wireless sensor patch for HR and BT by integrating sensor chip, wireless communication chip, and electrodes on the flexible boards that is covered with non-toxic, but skin-friendly adhesive patch. Our experimental results reveal that the flexible wireless sensor patch can efficiently detect early diseases by monitoring the HR and BT in real time.

Recently, various types of 3-D nonvolatile memory (NVM) devices have been researched to improve the integration density [1]-[3]. The NVM device of pillar structure can be considered as one of the candidates [4],[5]. When this is applied to a NAND flash memory array, bottom end of the device channel is connected to the bulk silicon. In this case, the current in vertical direction varies depending on the thickness of silicon channel. When the channel is thick, the difference of saturation current levels between on/off states of individual device is more obvious. On the other hand, when the channel is thin, the on/off current increases simultaneously whereas the saturation currents do not differ very much. The reason is that the channel potential barrier seen by drain electrons is lowered by read voltage on the opposite sidewall control gate. This phenomenon that can occur in 3-D structure devices due to proximity can be called gate-induced barrier lowering (GIBL). In this work, the dependence of GIBL on silicon channel thickness is investigated, which will be the criteria in the implementation of reliable ultra-small NVM devices.

One of 3-D devices to achieve high density arrays was adopted in this study, where source and drain junctions are formed along the silicon fin. The screening by adjacent high fins for large sensing margin makes it hard to ion-implant with high angle so that vertical ion implantation is inevitable. In this study, the dependency of current characteristics on doping profiles is investigated by 3-D numerical analysis. The position of concentration peak and the doping gradient are varied to look into the effects on driving currents. Through these analyses, the optimum condition of ion implantation for 3-D devices is estimated.

In performing the program operation of the NAND-type flash memory array, the program-inhibited cell is applied by a positive voltage at the gate, i.e., word-line (WL) on the floating channel while the program cell is applied by program voltage as the two ends, drain select line (DSL) and source select line (SSL), are turned on with grounded bit-line (BL). In this manner, the self-boosting of silicon channel to avoid unwanted program operation is made possible. As the flash memory device is aggressively scaled down and the channel doping concentration is increased accordingly, the coupling phenomena among WL, floating gate (FG)/storage node, and silicon channel, which are crucial factors in the self-boosting scheme, should be investigated more thoroughly. In this work, the dependences of self-boosting of channel potential on channel length and doping concentration in the 2-D conventional planar and 3-D FinFET NAND-type flash memory devices based on bulk-silicon are investigated by both 2-D and 3-D numerical device simulations. Since there hardly exists realistic ways of measuring the channel potential by physical probing, the series of simulation works are believed to offer practical insights in the variation of channel potential inside a flash memory device.