An 85 ns 16 Mb CMOS EPROM has been realized. It can be hard-ware configured as either 1 M 16 bits or 2 M 8 bits by controlling an input signal. An unique redundancy circuit, which includes two types of PROM cell fuses, allow testing the device completely before assembly. Bit-line division and tungsten polycide wordline are keys to achieve an 85 ns access time. A scaled EPROM cell of 3.6µm is realized with a 0.6 µm N-well CMOS technology with trench-self-aligned isolation and oxide-nitride-oxide interpoly dielectrics. The chip size is 7.1 17.1 mm.