In this paper, two types of improved CMRR CMOS OAs, N type and P type, without common-mode feedback and the cascode current mirrors, are proposed. The CMRR of proposed OAs are enhanced by compensating variations in tail bias current, caused by a common mode input signal, at the differential input stage, by means of feedforward controlled current source. Simulation results show that the CMRR of the proposed OAs are 20dB higher than that of conventional OAs.

A three-phase complex filter for a balanced three-phase analog signal processing is proposed. The proposed three-phase active-RC Tow-Thomas biquad complex filter can reduce total resistance by 10 percent, total capacitance by 25 percent, and power consumption by 22 percent compared to a conventional fully differential quadrature complex one.

A current-to-frequency converter using switched-current (SI) circuits is proposed. The SI integrator with a hold-and-reset switch can control integration by the output signals. In the proposed circuit the oscillation frequency can be controlled by the input current, and the circuit is operated in the current domain. This is verified by HSPICE simulations.

A CMOS current-mode continuous-time band-pass filter using the positive feedback Q (quality factor) - enhancement technique is presented in this paper. Q of the proposed filter can be mainly determined by the ratio of the two MOSFETs' transconductances in a Q-setting part, not by the ratio of two capacitance values similar to most of conventional band-pass filters. This filter can realize high Q value in spite of small chip area. Therefore, when higher value of Q is needed, the proposed filter does not need large capacitor which occupies large area on an IC chip. The proposed filter spends smaller chip area than the conventional one under the condition of Q>2. The proposed circuit is simulated by Spectre to confirm its characteristics.

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2µm N-well process with a 3 V supply are given.

A compact low-voltage CMOS exponential current-to-voltage converter free from transconductance parameter matching between NMOS and PMOS is proposed. The circuit is composed of level shift circuits and current mirrors. The SPICE simulation results show a 27 dB linear range with a linearity error of less than 1 dB.

A Switched-Opamp is a device in SC circuits for replacing switches with Opamps which operate like a switch. This technique can be acheived in very low voltage operation. In this paper, we present a design for a Switched-Opamp that can operate at a low supply voltage during the ON-phase and can maintain a high output impedance during the OFF-phase.

This paper presents a CMOS signal detection circuit for 2.5 Gb/s serial data communication system over FR-4 backplane. This overcomes characteristics deviation of full-wave rectifier-based simple power detection circuits due to data pattern and temperature by using an edge detector and a sample-hold circuit.

We propose a novel mobility reduction cancellation technique for an OTA (Operational Transconductance Amplifier). The proposed technique can be easily realized by using conventional OTAs. The proposed OTAs have good linearity. The simulation results show that the THD is less than 1% for 1.8 Vp-p at 3 V supply voltage.

This paper presents a novel method to increase an impedance of a current source. The proposed circuit with a cascode and gain-boosting configuration is also presented. The operation has been confirmed by simulation using a 0.18 µm CMOS technology.

In this paper, horizontal (where an opamp is shared in two adjacent stages) and vertical (where an opamp is shared across two paths) opamp sharing techniques for a two-path band-pass (BP) ΔΣ modulator are described, and input-feedforward two-path fourth-order BP ΔΣ modulators that have only two opamps are proposed. The proposed modulators are based on the horizontal or vertical opamp sharing technique. They can be realized with both a summation circuit using a switched capacitor (SC) network and a second-order high-pass filter (HPF) with a horizontal shared opamp or a double-sampling first-order HPF with a vertical shared opamp, which are based on an SC first-order HPF with an opamp. These techniques can reduce the number of opamps with no additional component and the chip area as well as realize lower power consumption.

A tail current source is often employed for many analog building blocks. It can limit the increase of excess power. It can also improve CMRR and PSRR. In this paper, we propose a very high output impedance tail current source for low voltage applications. The proposed tail current source has almost the same output impedance as the conventional cascode type tail current source in theory. Simulation results show that the output impedance of the proposed circuit becomes 1.28 GW at low frequencies. Applying the proposed circuit to a differential amplifier, the CMRR is enhanced by 66.7 dB, compared to the conventional differential amplifier. Moreover, the proposed circuit has the other excellent merit. The output stage of the proposed tail current source can operate at VDS(sat) and a quarter of VDS(sat) of the simple current source in theory and simulation, respectively. For example, in the simulation, when the reference current IREF is set to 100µA, the minimum voltage of the simple current source approximates 0.4 V, whereas that of the proposed current source approximates 0.1 V. Thus, the dynamic range can be enlarged by 0.3 V in this case. The value is still enough large value for low voltage applications. Hence, the proposed tail current source is suitable for low voltage applications.

The square-law characteristics of MOSFET in the saturation region have a parameter of threshold voltage VT. However, it introduces some complexities to the circuit design since it depends on kinds of MOS technology and cannot be controlled easily. In this paper, we show an equivalent MOSFET cell which has VT-programming capability and some application instances based on it. The simulation is carried out using CMOS 0.8 µm n-well technology and the results have shown the feasibility of the proposed structure.

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (1. 5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 µW, it has a sufficient input range, whereas conventional Wang's OTA needs 703 µW to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.

In this paper, we propose a universal biquad filter that can realize all types of 2nd-order functions, such as Low-pass Filters (LPF), High-Pass Filters (HPF), Band-Pass Filters (BPF), Band-Elimination Filters (BEF), and All-Pass Filters (APF). Also, the filter types can be programmable digitally with built-in switches. The proposed circuit can be realized by using a CMOS technology that is suitable for a mixed digital-analog LSI. In addition, the circuit can operate in high frequencies with a low power supply voltage because it is based on a current-mode circuit. Finally, the proposed circuit is simulated by PSpice to confirm its characteristics.

In this letter, a novel current-mode operational amplifier (COA) is proposed. The proposed COA can operate at 2 V (1 V) supply voltage. For high frequency operation it has only an npn transistor in signal path. Finally, SPICE simulation are shown to verify the performance of the proposed COA.

Two types of novel nVT level shift circuits based on the square law characteristics of MOSFETs have been proposed. These circuits generate VIN+nVT or VIN-nVT (where VT is a threshold voltage), if the input voltage is applied as the VIN. These circuits can be widely used in MOSFET characterization, compensating VT effect, VT measurement, level shifting, etc. Type 1 is directly derived from the nVT-sift circuit proposed by Wang. Type 2 can reduce a total chip area than type 1 and has a wider input range. SPICE simulations show that the proposed circuits have a very wide input range and a small power consumption.