A tail current source is often employed for many analog building blocks. It can limit the increase of excess power. It can also improve CMRR and PSRR. In this paper, we propose a very high output impedance tail current source for low voltage applications. The proposed tail current source has almost the same output impedance as the conventional cascode type tail current source in theory. Simulation results show that the output impedance of the proposed circuit becomes 1.28 GW at low frequencies. Applying the proposed circuit to a differential amplifier, the CMRR is enhanced by 66.7 dB, compared to the conventional differential amplifier. Moreover, the proposed circuit has the other excellent merit. The output stage of the proposed tail current source can operate at VDS(sat) and a quarter of VDS(sat) of the simple current source in theory and simulation, respectively. For example, in the simulation, when the reference current IREF is set to 100µA, the minimum voltage of the simple current source approximates 0.4 V, whereas that of the proposed current source approximates 0.1 V. Thus, the dynamic range can be enlarged by 0.3 V in this case. The value is still enough large value for low voltage applications. Hence, the proposed tail current source is suitable for low voltage applications.

The square-law characteristics of MOSFET in the saturation region have a parameter of threshold voltage VT. However, it introduces some complexities to the circuit design since it depends on kinds of MOS technology and cannot be controlled easily. In this paper, we show an equivalent MOSFET cell which has VT-programming capability and some application instances based on it. The simulation is carried out using CMOS 0.8 µm n-well technology and the results have shown the feasibility of the proposed structure.

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (1. 5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 µW, it has a sufficient input range, whereas conventional Wang's OTA needs 703 µW to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.

This paper describes the design and experiment results of a 25Gbps vertical-cavity surface emitting laser (VCSEL) driver circuit for a multi channel optical transmitter. To compensate for the non-linearity of the VCSEL and achieve high speed data rate communication, an asymmetric pre-emphasis technique is proposed for the VCSEL driver. An asymmetric pre-emphasis signal can be created by adjusting the duty ratio of the emphasis signal. The VCSEL driver adopts a double cascode connection that can apply a drive current from a high voltage DC bias and feed-forward compensation that can enhance the band-width for common-cathode VCSEL. For the design of the optical module structure, a two-tier low temperature co-fired ceramics (LTCC) package is adopted to minimize the wire bonding between the signal pad on the LTCC and the anode pad on the VCSEL. This structure and circuit reduces the simulated deterministic jitter from 12.7 to 4.1ps. A test chip was fabricated with the 65-nm standard CMOS process and demonstrated to work as an optical transmitter. An experimental evaluation showed that this VCSEL driver with asymmetric pre-emphasis reduced the total deterministic jitter up to 8.6ps and improved the vertical eye opening ratio by 3% compared with symmetric pre-emphasis at 25Gbps with a PRBS=29-1 test signal. The power consumption of the VCSEL driver was 3.0mW/Gbps/ch at 25Gbps. An optical transmitter including the VCSEL driver achieved 25-Gbps, 4-ch fully optical links.

In this paper, we propose a universal biquad filter that can realize all types of 2nd-order functions, such as Low-pass Filters (LPF), High-Pass Filters (HPF), Band-Pass Filters (BPF), Band-Elimination Filters (BEF), and All-Pass Filters (APF). Also, the filter types can be programmable digitally with built-in switches. The proposed circuit can be realized by using a CMOS technology that is suitable for a mixed digital-analog LSI. In addition, the circuit can operate in high frequencies with a low power supply voltage because it is based on a current-mode circuit. Finally, the proposed circuit is simulated by PSpice to confirm its characteristics.

C-C successive approximation register analog-to-digital converter (C-C SAR-ADC) is space-saving architecture compared to SAR-ADC with binary weighted capacitive digital-to-analog converter (CDAC). However, the accuracy of C-C SAR-ADC is degraded due to parasitic capacitance of floating nodes. This paper proposes an algorithm calibrating the non-linearity by γ-estimation to accurately estimate radix greater than 2 required to realize C-C SAR-ADC. Behavioral analyses show that the radix γ-estimation error become within 1.5, 0.4 and 0.1% in case of 8-, 10- and 12-bit resolution ADC, respectively. SPICE simulations show that the γ-estimation satisfies the requirement of 10-bit resolution C-C SAR-ADC. The C-C SAR-ADC using γ-estimation achieves 9.72bit of ENOB, 0.8/-0.5LSB and 0.5/-0.4LSB of DNL/INL.

In this letter, a novel current-mode operational amplifier (COA) is proposed. The proposed COA can operate at 2 V (1 V) supply voltage. For high frequency operation it has only an npn transistor in signal path. Finally, SPICE simulation are shown to verify the performance of the proposed COA.

Two types of novel nVT level shift circuits based on the square law characteristics of MOSFETs have been proposed. These circuits generate VIN+nVT or VIN-nVT (where VT is a threshold voltage), if the input voltage is applied as the VIN. These circuits can be widely used in MOSFET characterization, compensating VT effect, VT measurement, level shifting, etc. Type 1 is directly derived from the nVT-sift circuit proposed by Wang. Type 2 can reduce a total chip area than type 1 and has a wider input range. SPICE simulations show that the proposed circuits have a very wide input range and a small power consumption.

OTA (Operational Transconductance Amplifier) is a useful circuit in analog signal processing systems, especially in high-frequency applications. Important features of OTA are: infinite input impedance, electrically changeable transconductance (Gm), and much wider operation range without negative feedback such as in OPamp applications. The good linearity of OTA over wide input range is necessary to extend the application fields of OTA. Several techniques are developed to extend the input range with good linearity. In this paper, a highly-linear CMOS-OTA operating under 1 V power supply, is proposed. The concept of the proposed OTA is based on class-AB operation of two n-channel MOSFETs in the saturation region. By improving the input stage circuits, wide input range can be achieved. SPICE simulations are performed to verify the performance of the proposed OTA.

This paper describes 2.4-GHz-band front-end building circuits--a down conversion mixer (DCM), a dual-modulus divide-by-4/5 prescaler, a transmit/receive antenna switch (SW), a power amplifier (PA), and a low noise amplifier (LNA). They are fabricated using a standard bulk 0.18 µm CMOS process with a lower current consumption than bipolar circuits, and can operate at the low supply voltage of 1.8 V. Meshed-shielded pads are adopted for lower receiver circuit noise. Pads shielded by metals become cracked when they are bounded, therefore silicided active areas are used as shields instead of metals to avoid these cracks. The meshed shields achieve lower parasitic pad capacitors without parasitic resistors, and also act as dummy active areas. The proposed DCM has a high IP3 characteristic. The DCM has a cascode FET configuration and LO power is injected into the lower FET. By keeping the drain-source voltage of the upper transistor large, the nonlinearity of the drain-source transconductance is reduced and a low distortion DCM is realized. It achieves a higher input referred IP3 with a higher conversion gain for almost the same current consumption of a conventional single-balanced mixer. The output referred IP3 is higher 5.0 dB than the single-balanced mixer. The proposed dual-modulus prescaler employs a fully-differential technique to achieve stable operation. In order to avoid errors, the fully-differential circuit gives the logic voltage swing margins. In addition, the differential technique also reduces the noise effect from the supply voltage line because of the common-mode signal rejection. The maximum operating frequency is 3.0 GHz, and the one flip-flop power consumption normalized by the maximum operating frequency is 180 µW/GHz.

A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing. Thus, the CMOS circuit with a very low impedance terminal (VLIT circuit) is a useful analog building block to achieve the above purpose. The very low impedance terminal in the VLIT circuit is performed by a shunt-series feedback configuration. However, the feedback generates a problem of instability and/or oscillation at the same time. The problem can be removed by a phase compensation capacitor as known well, but the capacitor is not desirable for integrated circuits due to its large area. This paper proposes a new phase compensation technique for the VLIT circuit. The proposed technique does not need any capacitors to obtain a sufficient phase margin, and instead gives us the appropriate transistor sizes (Width and length of the gate). As a result, the VLIT circuit has an enough phase margin and operates stably.

In this paper, two types of improved CMRR CMOS OAs, N type and P type, without common-mode feedback and the cascode current mirrors, are proposed. The CMRR of proposed OAs are enhanced by compensating variations in tail bias current, caused by a common mode input signal, at the differential input stage, by means of feedforward controlled current source. Simulation results show that the CMRR of the proposed OAs are 20dB higher than that of conventional OAs.

A three-phase complex filter for a balanced three-phase analog signal processing is proposed. The proposed three-phase active-RC Tow-Thomas biquad complex filter can reduce total resistance by 10 percent, total capacitance by 25 percent, and power consumption by 22 percent compared to a conventional fully differential quadrature complex one.

A current-to-frequency converter using switched-current (SI) circuits is proposed. The SI integrator with a hold-and-reset switch can control integration by the output signals. In the proposed circuit the oscillation frequency can be controlled by the input current, and the circuit is operated in the current domain. This is verified by HSPICE simulations.

A CMOS current-mode continuous-time band-pass filter using the positive feedback Q (quality factor) - enhancement technique is presented in this paper. Q of the proposed filter can be mainly determined by the ratio of the two MOSFETs' transconductances in a Q-setting part, not by the ratio of two capacitance values similar to most of conventional band-pass filters. This filter can realize high Q value in spite of small chip area. Therefore, when higher value of Q is needed, the proposed filter does not need large capacitor which occupies large area on an IC chip. The proposed filter spends smaller chip area than the conventional one under the condition of Q>2. The proposed circuit is simulated by Spectre to confirm its characteristics.

A new gain enhancement technique for an operational amplifier (opamp) using a replica amplifier is presented to reduce a sensitivity of a gain mismatch between the main amplifier and the replica amplifier which limits a gain-enhancement factor in the conventional replica-amp techniques. In the proposed technique, the replica amplifier is used to only amplify an error voltage of the main amplifier. The outputs of the main amplifier and the replica amplifier are added to cancel the error voltage of the main amplifier. The proposed technique can also achieve a higher output voltage swing because the replica amplifier amplifies only the error voltage. In case of using a fully-differential common-source opamp for the main amplifier and a telescopic opamp for the replica amplifier, Monte Carlo simulation at 100 iterations shows that the proposed amplifier has almost the same gain variation with 15.5dB gain enhancement and about five times output voltage swing expanding for a supply voltage of 1.2V compared with the single closed-loop amplifier using the telescopic opamp.

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2µm N-well process with a 3 V supply are given.