1-4hit |
Kenichi AGAWA Shinichiro ISHIZUKA Hideaki MAJIMA Hiroyuki KOBAYASHI Masayuki KOIZUMI Takeshi NAGANO Makoto ARAI Yutaka SHIMIZU Asuka MAKI Go URAKAWA Tadashi TERADA Nobuyuki ITOH Mototsugu HAMADA Fumie FUJII Tadamasa KATO Sadayuki YOSHITOMI Nobuaki OTSUKA
A 2.4 GHz 0.13 µm CMOS transceiver LSI, supporting Bluetooth V2.1+enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40 and +90. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90 dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13 µm CMOS and operation at a low supply voltage of 1.5 V result in small area and low power consumption.
Kenichi AGAWA Yoshio HASHIMOTO Kazuhiko HIRAKAWA Noriaki SAKAMOTO Toshiaki IKOMA
We have systematically studied the characteristics of Si doping in GaAs grown on (311)A GaAs substrates by molecular beam epitaxy. The growth temperature dependence of Si doping has been investigated. It is found that the conduction-type sharply changes from p-type to n-type with decreasing growth temperature at a critical temperature of 430-480. The highest hole density obtained for uniformly doped layers was 1.51020 cm-3, while for δ-doped layers the sheet hole density as high as 2.61013 cm-2 was achieved. This is the highest hole density ever reported for δ-doped GaAs.
Daisuke MIYASHITA Kenichi AGAWA Hirotsugu KAJIHARA Kenichi SAMI Ichiro SETO Ryuichi FUJIMOTO Yasuo UNEKAWA
TransferJetTM is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer up to 522 Mbps within a few centimeters range. We present a fully integrated TransferJet SoC with a 4.48-GHz operating frequency and a 560-MHz signal bandwidth using a 65 nm CMOS technology. Baseband filtering techniques for a transmitter (TX) and a receiver (RX) are proposed in order to handle the ultra-wide bandwidth with low power consumption and small area. A programmable power attenuator (PAT) for precise output power is also proposed in this paper. The SoC achieves energy efficiencies of 0.19 nJ/bit and 0.43 nJ/bit for the TX and the RX, respectively. The RX sensitivity of -70 dBm for 522 Mbps data rate and the TX error vector magnitude (EVM) of -31 dB are achieved.
Toru TANZAWA Kenichi AGAWA Hiroyuki SHIBAYAMA Ryota TERAUCHI Katsumi HISANO Hiroki ISHIKURO Shouhei KOUSAI Hiroyuki KOBAYASHI Hideaki MAJIMA Toru TAKAYAMA Masayuki KOIZUMI Fumitoshi HATORI
A frequency drift of open-loop PLL is an issue for the direct-modulation applications such as Bluetooth transceiver. The drift mainly comes from a temperature variation of VCO during the transmission operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through the whole-chip thermal analysis. Moreover, a novel temperature-compensated VCO, employing a new biasing scheme, is proposed. The combination of these two techniques enables the power reduction of the transmitter by 33% without sacrificing the performance.