This paper discusses a power save management method appropriate for the features of the fiber-optic access network based on Passive Double Star (PDS) topology, where PDS termination processing LSIs for the Optical Network Unit (ONU) operate intermittently and the usage rate is low at the residential customer. We developed PDS termination processing LSIs for the ONU, performed power management, and evaluated the degree of consumed power.

We propose a propagation delay model for SRAM-based FPGAs. It is a simplified Elmore delay model with a linear fan-out function. Therefore, the computational complexity is small. In order to ensure calculation accuracy, the model parameters are extracted from real layout data. The average model error is 4% compared to actual delays. The model is applicable for delay estimation in a router and as a tool for static calculation of critical path delay.

This paper presents an FPGA architecture for high-speed systems, such as next-generation B-ISDN telecommunications systems. Such a system requires an LSI in which an over-10K-gate circuit can be implemented and that has a clock cycle rate of 80MHz. So far, the FPGA architecture has only been discussed in terms of its circuit structure. In contrast we consider the circuit structure of the FPGA along with the performance of its dedicated CAD system. We evaluate several FPGA logic-element structures with a technology mapping method. From these experiments, a multiplexor-based logic-element is found to be suitable for implementing such a high-speed circuit using the BDD-based technology mapping method. In addition, we examine how to best utilize the characteristics of the selected logic-cell structure in designing the wiring structure. It is found that the multiplexor-based cell can be connected efficiently in a clustered wiring structure.

We have developed a Field-Programmable Multi-Chip Module (FPMCM) whose component is the telecommunication-oriented FPGAs, called PROTEUS. The module consists of 3 3 PROTEUS FPGAs and its size is 114 mm square. Each PROTEUS chip is mounted on the MCM substrate using Tape Automated Bonding (TAB) technology so as to minimize the size of the MCM and the production cost. The interconnection topology among the FPGAs is a simple mesh. However, the connection can be changed logically, because PROTEUS itself has a special inter-I/O bypass resource in it. Using this mechanism, the interchip connection delay can be reduced without sacrificing the flexibility, compared to the previous FPMCM implementation using some other interconnection switches which often have a large propagation delay. The interchip connection delay is 200 ps. We have also developed a rapid prototyping system comprising several MCMs, and implemented telecommunication circuits in it.