The design of high performance-circuits using Field-Programmable Gate Arrays (FPGAs) requires a balance between the FPGA's architecture and CAD algorithms. Conventional FPGAs and CAD algorithms are developed independently, which makes it difficult to implement application circuits. To solve this problem, we developed a CAD-verified FPGA whose architecture was designed at the same time as the CAD algorithms. This paper shows how a CAD-verified FPGA architecture can simplify a routing algorithm. The algorithm is studied in terms of computational complexity and is simplified using the properties of our FPGA (switch module structure and the number of routing resources). The routing algorithm is almost one hundred times faster than that of the conventional router, and the quality of its circuits is also improved.

This innovative traffic-monitoring-system makes it possible to observe data-communication traffic on an oscilloscope-style display. It provides an efficient way of evaluating streaming-data quality. The monitoring system has a high time-resolution traffic value sampling function and a real-time data representation/recording mechanism that operate in synchrony. The user can directly evaluate the traffic shape with the monitoring system. In this paper, after describing the concept of the traffic monitoring system, we will describe a prototype built with programmable network equipment called A-BOX. We will then review a performance evaluation and other experimental results to prove that our monitoring system is suitable for video streaming.

We have developed a Field-Programmable Multi-Chip Module (FPMCM) whose component is the telecommunication-oriented FPGAs, called PROTEUS. The module consists of 3 3 PROTEUS FPGAs and its size is 114 mm square. Each PROTEUS chip is mounted on the MCM substrate using Tape Automated Bonding (TAB) technology so as to minimize the size of the MCM and the production cost. The interconnection topology among the FPGAs is a simple mesh. However, the connection can be changed logically, because PROTEUS itself has a special inter-I/O bypass resource in it. Using this mechanism, the interchip connection delay can be reduced without sacrificing the flexibility, compared to the previous FPMCM implementation using some other interconnection switches which often have a large propagation delay. The interchip connection delay is 200 ps. We have also developed a rapid prototyping system comprising several MCMs, and implemented telecommunication circuits in it.