A gate oxide excess current model is described based on the phonon-assisted tunneling process of electrons into neutral traps. The influence on local electric field of charge of electrons trapped by neutral traps in gate oxide is simulated using a two-dimensional device simulator into which the new model is incorporated. FN current is suppressed with an increase in the neutral trap density to over 1019 cm-3. The calculated results reflect the endurance characteristics of flash memories in which erase/write operation speed depends on FN current.

A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm2 cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm2 cell size for a 0.5 µm 64 Mbit flash memory, is described.