Improved Array Architectures of DINOR for 0.5 µm 32 M and 64 Mbit Flash Memories

Hiroshi ONODA; Yuichi KUNORI; Kojiro YUZURIHA; Shin-ichi KOBAYASHI; Kiyohiko SAKAKIBARA; Makoto OHI; Atsushi FUKUMOTO; Natsuo AJIKA; Masahiro HATANAKA; Hirokazu MIYOSHI

Improved Array Architectures of DINOR for 0.5 µm 32 M and 64 Mbit Flash Memories

Hiroshi ONODA, Yuichi KUNORI, Kojiro YUZURIHA, Shin-ichi KOBAYASHI, Kiyohiko SAKAKIBARA, Makoto OHI, Atsushi FUKUMOTO, Natsuo AJIKA, Masahiro HATANAKA, Hirokazu MIYOSHI

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A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm² cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm² cell size for a 0.5 µm 64 Mbit flash memory, is described.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.8 pp.1279-1286

Publication Date: 1994/08/25

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Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)

Category: Non-volatile Memory

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Hiroshi ONODA, Yuichi KUNORI, Kojiro YUZURIHA, Shin-ichi KOBAYASHI, Kiyohiko SAKAKIBARA, Makoto OHI, Atsushi FUKUMOTO, Natsuo AJIKA, Masahiro HATANAKA, Hirokazu MIYOSHI, "Improved Array Architectures of DINOR for 0.5 µm 32 M and 64 Mbit Flash Memories" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 8, pp. 1279-1286, August 1994, doi: .
Abstract: A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm² cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm² cell size for a 0.5 µm 64 Mbit flash memory, is described.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_8_1279/_p

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@ARTICLE{e77-c_8_1279,
author={Hiroshi ONODA, Yuichi KUNORI, Kojiro YUZURIHA, Shin-ichi KOBAYASHI, Kiyohiko SAKAKIBARA, Makoto OHI, Atsushi FUKUMOTO, Natsuo AJIKA, Masahiro HATANAKA, Hirokazu MIYOSHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Improved Array Architectures of DINOR for 0.5 µm 32 M and 64 Mbit Flash Memories},
year={1994},
volume={E77-C},
number={8},
pages={1279-1286},
abstract={A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm² cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm² cell size for a 0.5 µm 64 Mbit flash memory, is described.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - Improved Array Architectures of DINOR for 0.5 µm 32 M and 64 Mbit Flash Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 1279
EP - 1286
AU - Hiroshi ONODA
AU - Yuichi KUNORI
AU - Kojiro YUZURIHA
AU - Shin-ichi KOBAYASHI
AU - Kiyohiko SAKAKIBARA
AU - Makoto OHI
AU - Atsushi FUKUMOTO
AU - Natsuo AJIKA
AU - Masahiro HATANAKA
AU - Hirokazu MIYOSHI
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1994
AB - A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm² cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm² cell size for a 0.5 µm 64 Mbit flash memory, is described.
ER -