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Kousuke KATAYAMA Atsushi IWATA
In this paper, we propose a novel pulse-coupled neural network (PCNN) simulator using a programmable gate array (PGA) technique. The simulator is composed of modified phase-locked loops (PLLs) and a programmable gate array (PGA). The PLL, which is modified by the addition of multiple inputs and multiple feedbacks, works as a neuron. The PGA, which controls the network connection, works as nodes of dendritic trees. This simulator, which has 16 neurons and 32 32 network connections, is designed on a chip (4.73mm 4.73mm), and its basic operations such as synchronization, an oscillatory associative memory, and FM interactions are confirmed using circuit simulator SPICE.
Kousuke KATAYAMA Atsushi IWATA Takashi MORIE Makoto NAGATA
A circuit that carries out an Hadamard transform of an input image using the pulse width modulation technique is proposed. The proposed circuit architecture realizes the function of an Hadamard transform with a full-size pixel image. A test chip that we designed and fabricated integrates 64 64 pixels in a 4.9 mm 4.9 mm area, with 0.35 µm CMOS technology. The functional operation and linearity of this chip are measured. An image processing application utilizing this chip is demonstrated.
Kousuke KATAYAMA Atsushi IWATA
This paper proposes a high-resolution CMOS image sensor, which has Hadamard transform function. This Hadamard transform circuit consists of two base generators, an array of pixel circuits, and analog-to-digital converters. In spite of simple composition, a base generator outputs a variety of bases, a pixel circuit calculates a two-dimensional base from one-dimensional bases and outputs values to common line for current addition, and analog-to-digital converter converts current value to digital value and stabilize a common line voltage for elimination of parasitic capacitance. We simulated these circuit elements and optimized using SPICE. Basic operations of this Hadamard transform circuit are also confirmed by simulation. A 256 256 pixel test chip was designed in 4.73 mm 4.73 mm area with 0.35 µm CMOS technology. A fill factor of this chip is 42% and dynamic range is 55.6 [dB]. Functions of this chip are Hadamard transform, Harr transform, projection, obtaining center of gravity, and so on.