This paper describes an overview of overall carrier-grade Ethernet technologies for next generation wide area Ethernet. In recent years, from access network to metro and core network, we can find many areas where communication services are provided by Ethernet technologies. This comes from the fact that operational efficiency and economical efficiency of Ethernet are far better than that of conventional wide area communication technologies such as SONET and ATM. On the other hand, carrier-grade reliability, operations-administration-maintenance (OAM) and quality of service (QoS) are inferior to SONET and ATM. Various standard schemes in IEEE 802 and ITU-T and vendors' proprietary schemes can leave various approaches to solve these problems. In this paper, the author explains a basic architecture of wide area Ethernet service (Q-in-Q tagging for metro network and Mac-in-Mac encapsulation for core network) at first. Various switch control technologies are then discussed which are deployed or are under evaluation in order to improve (i) reliability (i.e., resiliency) to protect subscribers against network failures, (ii) OAM for providers to perform fault and performance management, and (iii) QoS to guarantee subscriber's service level agreement between a carrier and a subscriber. Finally, a new switching architecture, Global Open Ethernet (GOE), is also introduced as one of promising approaches to realize a next generation carrier-grade Ethernet.

This paper presents a neural circuit using PWM technique based on an analog-digital merged circuit architecture. Some new PWM circuit techniques are proposed. A bipolar-weighted summation circuit is described which attains 8-bit precision in SPICE simulation at 5 V supply voltage by compensating parasitic capacitance effects. A high performance differential-type latch comparator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0.6µm CMOS process. The measurement results demonstrate that the overall precision in the weighted summation and the sigmoidal transformation is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation.

This paper describes the analysis of integrated optical waveguides using Finite-Difference Time-Domain (FDTD) method, and proposes the design methodology for low loss waveguide components: corner bends and branches. In order to integrate optical waveguides with Si VLSI technologies on a chip, the compact bends or branches are necessary. Since the optical power radiation from a bend or a branch point depends on the waveguide shapes, an accurate analysis of guided wave behavior is required. For the purpose we adopted the FDTD method which can analyze optical waveguides with a large variation of refractive index and arbitrary shape. Proposed design concept is to have all waveguides transmit only the fundamental mode and to design whole waveguides based on the fundamental mode transfer characteristics. For this design concept, waveguide components are required to have not only low radiation loss but also a little mode shift from the fundamental mode. The bend using the double-reflection mirrors and the branch using a slit are proposed for suppressing the mode shift and improving radiation loss. By the FDTD analysis, the following results have been obtained. The radiation loss and mode shift of double reflection bend are 1% and 4%, and those of the slit branch are 2% and 5%, respectively, in 2 µm width waveguide.

We present a new multi-path routing methodology, MLB-routing, that is based on the multinomial logit model, which is well known in the random utility field. The key concept of the study is to set multiple paths from the origin to the destination, and distribute packets in accordance with multinomial logit type probability. Since MLB-routing is pure multi-path routing, it reduces the convergence on some links and increases bandwidth utilization in the network. Unlike existing multi-path routing schemes, which pre-set alternate paths, the proposed method can dynamically distribute packets to every possible path and thus is more efficient. Furthermore, it should be mentioned that this methodology can be implemented as either a link-state protocol or a distance-vector protocol. Therefore, it well supports the existing Internet. Simulations show that this methodology raises network utilization and significantly reduces end-to-end delay and jitter.

An integrate-and-fire-type spiking feedback network is discussed in this paper. In our spiking neuron model, analog information expressing processing results is given by the relative relation of spike firing. Therefore, for spiking feedback networks, all neurons should fire (pseudo-)periodically. However, an integrate-and-fire-type neuron generates no spike unless its internal potential exceeds the threshold. To solve this problem, we propose negative thresholding operation. In this paper, this operation is achieved by a global excitatory unit. This unit operates immediately after receiving the first spike input. We have designed a CMOS spiking feedback network VLSI circuit with the global excitatory unit for Hopfield-type associative memory. The circuit simulation results show that the network achieves correct association operation.

Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90 nm CMOS technology. A 2 Vpp input voltage range and 50 µW power consumption were achieved by the measurements with a 0.5 V supply. High accuracy of 62 dB SNR was obtained at signal bandwidth of 120 kHz.

In this paper, we propose a novel pulse-coupled neural network (PCNN) simulator using a programmable gate array (PGA) technique. The simulator is composed of modified phase-locked loops (PLLs) and a programmable gate array (PGA). The PLL, which is modified by the addition of multiple inputs and multiple feedbacks, works as a neuron. The PGA, which controls the network connection, works as nodes of dendritic trees. This simulator, which has 16 neurons and 32 32 network connections, is designed on a chip (4.73mm 4.73mm), and its basic operations such as synchronization, an oscillatory associative memory, and FM interactions are confirmed using circuit simulator SPICE.

A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched op-amp. The low-noise amplifier fabricated in a 0.18-µm CMOS technology achieved 50-nV/Hz input noise at 1-MHz chopping and 0.5-mW power consumption at 1-V supply voltage.

This paper proposes a new associative memory architecture using stochastic behavior in single electron tunneling (SET) devices. This memory stochastically extracts the pattern most similar to the input key pattern from the stored patterns in two matching modes: the voltage-domain matching mode and the time-domain one. In the former matching mode, ordinary associative memory operation can be performed. In the latter matching mode, a purely stochastic search can be performed. Even in this case, by repeating numerous searching trials, the order of similarity can be obtained. We propose a circuit using SET devices based on this architecture and demonstrate its basic operation with a simulation. By feeding the output pattern back to the input, this memory retrieves slightly dissimilar patterns consecutively. This function may be the key to developing highly intelligent information processing systems close to the human brain.

Substrate-coupling equivalent circuits can be derived for arbitrary isolation structures by F-matrix computation. The derived netlist represents a unified impedance network among multiple sites on a chip surface as well as internal nodes of isolation structures and can be applied with SPICE simulation to evaluate isolation strengths. Geometry dependency of isolation attributes to layout parameters such as area, width, and location distance. On the other hand, structural dependency arises from vertical impurity concentration specific to p+/n+ diffusion and deep n-well. Simulation-based prototyping of isolation structures can include all these dependences and strongly helps establish an isolation strategy against high-frequency substrate coupling in a given technology. The analysis of isolation strength provided by p+/n+ guard ring, deep n-well guard ring as well as deep n-well pocket well explains S21 measurements performed on high-frequency test structures targeting 5 GHz bandwidth, that was formed in a 0.25-µm CMOS high frequency.

This paper proposes a new method for image segmentation and extraction using nonlinear cellular networks. Flexible segmentation of complicated natural scene images is achieved by using resistive-fuse networks, and each segmented regions is extracted by nonlinear oscillator networks. We also propose a nonlinear cellular network circuit implementing both resistive-fuse and oscillator dynamics by using pulse-modulation techniques. The basic operation of the nonlinear network circuit is confirmed by SPICE simulation. Moreover, the 1010-pixel image segmentation and extraction are demonstrated by high-speed circuit simulation.

The concept of stochastic association has originally been proposed in relation to single-electron devices having stochastic behavior due to quantum effects. Stochastic association is one of the promising concepts for future VLSI systems that exceed the conventional digital systems based on deterministic operation. This paper proposes a CMOS stochastic associative processor using PWM (pulse-width modulation) chaotic signals. The processor stochastically extracts one of the stored binary patterns depending on the order of similarity to the input. We confirms stochastic associative processing operation by experiments for digit pattern association using the CMOS test chip.

Progress of roles and schemes of calibration techniques in data converters are reviewed. Correction techniques of matching error and nonlinearity in analog circuits have been developed by digital assist using high-density and low-power digital circuits. The roles of the calibration are not only to improve accuracy but also to reduce power dissipation and chip area. Among various calibration schemes, the background calibration has significant advantages to achieve robustness to fast ambient change. Firstly the nonlinearity calibrations for pipeline ADCs are reviewed. They have required new solutions for redundancy of the circuits, an error estimation algorithm and reference signals. Currently utilizing the calibration techniques, the performance of 100 Msps and 12 bit has been achieved with 10 mW power dissipation. Secondly the background calibrations of matching error in flash ADC and DAC with error feedback to the analog circuits are described. The flash ADC utilizes the comparator offset correction with successive approximation algorithm. The DAC adopts a self current matching scheme with an analog memory. Measured dissipation power of the ADC is 0.38 mW at 300 MHz clock. Effects of the background calibration to suppress crosstalk noise are also discussed.

Intelligent robot control systems based on multiprocessors, sensors, and actuators require a flexible network for communicating various types of real-time data (e.g. sensing data, interrupt signals). Furthermore, serial data transfer implemented using a few wiring lines is also required. Therefore, a CDMA serial communication interface with a new two-step synchronization technique is proposed to counter these problems. The transmitter and receiver fabricated by 0.25 µm digital CMOS technology achieve 2.7 Gcps (gigachips per second) and can multiplex 7 communication channels.

Chip-level substrate coupling analysis uses F-matrix computation with slice-and-stack execution to include highly concentrated substrate resistivity gradient. The technique that has been applied to evaluation of device-level isolation structures against substrate coupling is now developed into chip-level substrate noise analysis. A time-series divided parasitic capacitance (TSDPC) model is equivalent to a transition controllable noise source (TCNS) circuit that captures noise generation in a CMOS digital circuit. A reference structure incorporating TCNS circuits and an array of on-chip high precision substrate noise monitors provides a basis for the verification of chip-level analysis of substrate coupling in a given technology. Test chips fabricated in two different wafer processings of 0.30-µm and 0.18-µm CMOS technologies demonstrate the universal availability of the proposed analysis techniques. Substrate noise simulation achieves no more than 3 dB discrepancy in peak amplitude compared to measurements with 100-ps/100-µV resolution, enabling precise evaluation of the impacts of the distant placements of sensitive devices from sources of noise as well as application of guard ring/band structures.

A circuit that carries out an Hadamard transform of an input image using the pulse width modulation technique is proposed. The proposed circuit architecture realizes the function of an Hadamard transform with a full-size pixel image. A test chip that we designed and fabricated integrates 64 64 pixels in a 4.9 mm 4.9 mm area, with 0.35 µm CMOS technology. The functional operation and linearity of this chip are measured. An image processing application utilizing this chip is demonstrated.

This paper proposes a high-resolution CMOS image sensor, which has Hadamard transform function. This Hadamard transform circuit consists of two base generators, an array of pixel circuits, and analog-to-digital converters. In spite of simple composition, a base generator outputs a variety of bases, a pixel circuit calculates a two-dimensional base from one-dimensional bases and outputs values to common line for current addition, and analog-to-digital converter converts current value to digital value and stabilize a common line voltage for elimination of parasitic capacitance. We simulated these circuit elements and optimized using SPICE. Basic operations of this Hadamard transform circuit are also confirmed by simulation. A 256 256 pixel test chip was designed in 4.73 mm 4.73 mm area with 0.35 µm CMOS technology. A fill factor of this chip is 42% and dynamic range is 55.6 [dB]. Functions of this chip are Hadamard transform, Harr transform, projection, obtaining center of gravity, and so on.

A merged analog-digital circuit architecture is proposed for implementing intelligence in SoC systems. Pulse modulation signals are introduced for time-domain massively parallel analog signal processing, and also for interfacing analog and digital worlds naturally within the SoC VLSI chip. Principles and applications of pulse-domain linear arithmetic processing are explored, and the results are expanded to the nonlinear signal processing, including an arbitrary chaos generation and continuous-time dynamical systems with nonlinear oscillation. Silicon implementations of the circuits employing the proposed architecture are fully described.