A low power impulse radio ultra-wideband (IR-UWB) receiver for DC-960 MHz band is proposed in this paper. The proposed receiver employs multiple DC power-free charge-domain sampling correlators to eliminate the need for phase synchronization. To alleviate BER degradation due to an increased charge injection in a subtraction operation in the sampling correlator than that of an addition operation, a comparator with variable threshold (=offset) voltage is used, which enables an addition-only operation. The developed receiver fabricated in 1.2 V 65 nm CMOS achieves the lowest energy consumption of 17.6 pJ/bit at 100 Mbps in state-of-the-art correlation-based UWB receivers.

A 0.6-V voltage shifter and a 0.6-V clocked comparator are presented for sampling correlation-based impulse radio UWB receiver. The voltage shifter is used for a novel split swing level scheme-based CMOS transmission gate which can reduce the power consumption by four times. Compared to the conventional voltage shifter, the proposed voltage shifter can reduce the required capacitance area by half and eliminate the non-overlapping complementary clock generator. The proposed 0.6-V clocked comparator can operate at 100-MHz clock with the voltage shifter. To reduce the power consumption of the conventional continuous-time comparator based synchronization control unit, a novel clocked-comparator based control unit is presented, thereby achieving the lowest energy consumption of 3.9 pJ/bit in the correlation-based UWB receiver with the 0.5 ns timing step for data synchronization.

A novel DC-to-960 MHz impulse radio ultra-wideband (IR-UWB) transceiver based on threshold detection technique is developed. It features a digital pulse-shaping transmitter, a DC power-free pulse discriminator and an error-recovery phase-frequency detector. The developed transceiver in 90 nm CMOS achieves the lowest energy consumption of 2.2 pJ/bit transmitter and 1.9 pJ/bit receiver at 100 Mbps in the UWB transceivers.

Parametric resonance based solutions for sub-gigahertz radio frequency transceiver with 0.3V supply voltage are proposed in this paper. As an implementation example, a 0.3V 720µW variation-tolerant injection-locked frequency multiplier is developed in 90nm CMOS. It features a parametric resonance based multi-phase synthesis scheme, thereby achieving the lowest supply voltage with -110dBc@ 600kHz phase noise and 873MHz-1.008GHz locking range in state-of-the-art frequency synthesizers.

A 315 MHz power-gated ultra low power transceiver for wireless sensor network is developed in 40 nm CMOS. The developed transceiver features an injection-locked frequency multiplier for carrier generation and a power-gated low noise amplifier with current second-reuse technique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby achieves 11 µW power consumption at 315 MHz. The proposed low noise amplifier achieves the lowest power consumption of 8.4 µW with 7.9 dB noise figure and 20.5 dB gain in state-of-the-art designs.