Parametric Resonance Based Frequency Multiplier for Sub-Gigahertz Radio Receiver with 0.3V Supply Voltage

Lechang LIU; Keisuke ISHIKAWA; Tadahiro KURODA

doi:10.1587/transele.E97.C.505

Parametric Resonance Based Frequency Multiplier for Sub-Gigahertz Radio Receiver with 0.3V Supply Voltage

Lechang LIU, Keisuke ISHIKAWA, Tadahiro KURODA

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Parametric resonance based solutions for sub-gigahertz radio frequency transceiver with 0.3V supply voltage are proposed in this paper. As an implementation example, a 0.3V 720µW variation-tolerant injection-locked frequency multiplier is developed in 90nm CMOS. It features a parametric resonance based multi-phase synthesis scheme, thereby achieving the lowest supply voltage with -110dBc@ 600kHz phase noise and 873MHz-1.008GHz locking range in state-of-the-art frequency synthesizers.

Publication: IEICE TRANSACTIONS on Electronics Vol.E97-C No.6 pp.505-511

Publication Date: 2014/06/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E97.C.505

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)

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Authors

Lechang LIU
  Keio University
Keisuke ISHIKAWA
  Keio University
Tadahiro KURODA
  Keio University

Keyword

parametric resonance, injection-locked frequency multiplier, phase noise, radio frequency (RF)

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Lechang LIU, Keisuke ISHIKAWA, Tadahiro KURODA, "Parametric Resonance Based Frequency Multiplier for Sub-Gigahertz Radio Receiver with 0.3V Supply Voltage" in IEICE TRANSACTIONS on Electronics, vol. E97-C, no. 6, pp. 505-511, June 2014, doi: 10.1587/transele.E97.C.505.
Abstract: Parametric resonance based solutions for sub-gigahertz radio frequency transceiver with 0.3V supply voltage are proposed in this paper. As an implementation example, a 0.3V 720µW variation-tolerant injection-locked frequency multiplier is developed in 90nm CMOS. It features a parametric resonance based multi-phase synthesis scheme, thereby achieving the lowest supply voltage with -110dBc@ 600kHz phase noise and 873MHz-1.008GHz locking range in state-of-the-art frequency synthesizers.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.505/_p

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@ARTICLE{e97-c_6_505,
author={Lechang LIU, Keisuke ISHIKAWA, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Parametric Resonance Based Frequency Multiplier for Sub-Gigahertz Radio Receiver with 0.3V Supply Voltage},
year={2014},
volume={E97-C},
number={6},
pages={505-511},
abstract={Parametric resonance based solutions for sub-gigahertz radio frequency transceiver with 0.3V supply voltage are proposed in this paper. As an implementation example, a 0.3V 720µW variation-tolerant injection-locked frequency multiplier is developed in 90nm CMOS. It features a parametric resonance based multi-phase synthesis scheme, thereby achieving the lowest supply voltage with -110dBc@ 600kHz phase noise and 873MHz-1.008GHz locking range in state-of-the-art frequency synthesizers.},
keywords={},
doi={10.1587/transele.E97.C.505},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - Parametric Resonance Based Frequency Multiplier for Sub-Gigahertz Radio Receiver with 0.3V Supply Voltage
T2 - IEICE TRANSACTIONS on Electronics
SP - 505
EP - 511
AU - Lechang LIU
AU - Keisuke ISHIKAWA
AU - Tadahiro KURODA
PY - 2014
DO - 10.1587/transele.E97.C.505
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2014
AB - Parametric resonance based solutions for sub-gigahertz radio frequency transceiver with 0.3V supply voltage are proposed in this paper. As an implementation example, a 0.3V 720µW variation-tolerant injection-locked frequency multiplier is developed in 90nm CMOS. It features a parametric resonance based multi-phase synthesis scheme, thereby achieving the lowest supply voltage with -110dBc@ 600kHz phase noise and 873MHz-1.008GHz locking range in state-of-the-art frequency synthesizers.
ER -