A 3.3-V 512-k 18-b 2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm2, which is the same die size as our conventional DRAM, has been achieved with 0.50-µm CMOS process technology.

Fiber-optic access system integration is the key to providing various kinds of services to home users. The combination of ATM- and SCM-PON systems is essential to support a high-speed data service and analog/digital video distribution services. From this viewpoint, a frequency-division- multiplexing technique for digital baseband and subcarrier multiplexed signals is required to achieve system integration. However, system integration for these two access systems has not been fully investigated yet. The SCM-PON system, which uses a super wideband optical FM converter, will enable these two different kinds of access system (ATM and SCM) to be integrated. In this paper, we describe experimentally obtained results for frequency- division-multiplexed signals consisting of digital baseband and subcarrier- multiplexed signals. The experiments were carried out using a 622-Mb/s baseband signal and an FM-converted signal containing AM and 64QAM signals. The experimental results reveal that the inter-channel interference between the digital baseband and FM-converted signals restricts the number of subcarriers for AM and 64QAM. With an intermediate frequency of 3 GHz for the FM-converted signal, an FDM signal consisting of 622-Mb/s baseband, 30 carriers of 64QAM, and 11 carriers of AM was successfully transmitted.