250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture

Yasuhiro TAKAI; Mamoru NAGASE; Mamoru KITAMURA; Yasuji KOSHIKAWA; Naoyuki YOSHIDA; Yasuaki KOBAYASHI; Takashi OBARA; Yukio FUKUZO; Hiroshi WATANABE

250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture

Yasuhiro TAKAI, Mamoru NAGASE, Mamoru KITAMURA, Yasuji KOSHIKAWA, Naoyuki YOSHIDA, Yasuaki KOBAYASHI, Takashi OBARA, Yukio FUKUZO, Hiroshi WATANABE

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A 3.3-V 512-k 18-b 2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm², which is the same die size as our conventional DRAM, has been achieved with 0.50-µm CMOS process technology.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.756-761

Publication Date: 1994/05/25

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Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

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Yasuhiro TAKAI
Mamoru NAGASE
Mamoru KITAMURA
Yasuji KOSHIKAWA
Naoyuki YOSHIDA
Yasuaki KOBAYASHI
Takashi OBARA
Yukio FUKUZO
Hiroshi WATANABE

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Yasuhiro TAKAI, Mamoru NAGASE, Mamoru KITAMURA, Yasuji KOSHIKAWA, Naoyuki YOSHIDA, Yasuaki KOBAYASHI, Takashi OBARA, Yukio FUKUZO, Hiroshi WATANABE, "250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 5, pp. 756-761, May 1994, doi: .
Abstract: A 3.3-V 512-k 18-b 2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm², which is the same die size as our conventional DRAM, has been achieved with 0.50-µm CMOS process technology.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_5_756/_p

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@ARTICLE{e77-c_5_756,
author={Yasuhiro TAKAI, Mamoru NAGASE, Mamoru KITAMURA, Yasuji KOSHIKAWA, Naoyuki YOSHIDA, Yasuaki KOBAYASHI, Takashi OBARA, Yukio FUKUZO, Hiroshi WATANABE, },
journal={IEICE TRANSACTIONS on Electronics},
title={250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture},
year={1994},
volume={E77-C},
number={5},
pages={756-761},
abstract={A 3.3-V 512-k 18-b 2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm², which is the same die size as our conventional DRAM, has been achieved with 0.50-µm CMOS process technology.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - 250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 756
EP - 761
AU - Yasuhiro TAKAI
AU - Mamoru NAGASE
AU - Mamoru KITAMURA
AU - Yasuji KOSHIKAWA
AU - Naoyuki YOSHIDA
AU - Yasuaki KOBAYASHI
AU - Takashi OBARA
AU - Yukio FUKUZO
AU - Hiroshi WATANABE
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - A 3.3-V 512-k 18-b 2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm², which is the same die size as our conventional DRAM, has been achieved with 0.50-µm CMOS process technology.
ER -