It is often desired to change the cutoff frequencies of digital filters in some applications like digital electronic instruments. This paper proposes a design of variable lowpass digital filters with wider ranges of cutoff frequencies than conventional designs. Wave digital filters are used for the prototypes of variable filters. The proposed design is based on the frequency scaling in the s-domain, while the conventional ones are based on the z-domain lowpass-to-lowpass transformations. The first-order approximation by the Taylor series expansion is used to make multiplier coefficients in a wave digital filters obtained from a frequency-scaled LC filter become linear functions of the scaling parameter, which is similar to the conventional design. Furthermore this paper discusses the reduction of the approximation error. The curvature is introduced as the figure of the quality of the first-order approximation. The use of the second-order approximation to large-curvature multiplier coefficients instead of the first-order one is proposed.

It is important to optimize aggregation schemes for heterogeneous wireless networks for maximizing communication throughput utilizing any available radio access networks. In the heterogeneous networks, differences of the quality of service (QoS), such as throughput, delay and packet loss rate, of the networks makes difficult to maximize the aggregation throughput. In this paper, we firstly analyze influences of such differences in QoS to the aggregation throughput, and show that it is possible to improve the throughput by adjusting the parameters of an aggregation system. Since manual parameter optimization is difficult and takes much time, we propose an autonomous parameter tuning scheme using a machine learning algorithm for the heterogeneous wireless network aggregation. We implement the proposed scheme on a heterogeneous cognitive radio network system. The results on our experimental network with network emulators show that the proposed scheme can improve the aggregation throughput better than the conventional schemes. We also evaluate the performance using public wireless network services, such as HSDPA, WiMAX and W-CDMA, and verify that the proposed scheme can improve the aggregation throughput by iterating the learning cycle even for the public wireless networks. Our experimental results show that the proposed scheme achieves twice better aggregation throughput than the conventional schemes.

We report the successful operation of a low-power arithmetic logic unit (ALU) based on a low-voltage rapid single-flux-quantum (LV-RSFQ) logic circuit, whereby a dc bias current is fed to circuits from lowered constant-voltage sources through small resistors. Both the static and dynamic energy consumptions are reduced because of the reduction in the amplitudes of voltage pulses across the Josephson junctions, with a trade-off of slightly slower switching speeds. The designed bias voltage was set to 0.25mV, which is one-tenth that of our standard RSFQ circuit design. We investigated several issues related to such low-voltage operation, including margins and timing design. To achieve successful operation, we tuned the circuit parameters in the logic gate design and carefully controlled the timing by considering the interference of pulse signals. We show test results for the low-voltage ALU in on-chip high-speed testing. The circuit was fabricated using the AIST Nb/AlOx/Nb Advanced Process with a critical current density of 10kA/cm2. We verified that arithmetic and logical operations were correctly implemented and obtained dc bias margins of 18% at a target clock frequency of 20GHz and achieved a maximum clock frequency of 28GHz with a power consumption of 28µW. These experimental results indicate energy efficiency of 3.6 times that of the standard RSFQ circuit design.

The locally one-dimensional finite-difference time-domain (FDTD) method in cylindrical coordinates is extended to a frequency-dependent version. The fundamental scheme is utilized to perform matrix-operator-free formulations in the right-hand sides. For the analysis of surface plasmon polaritons propagating along a plasmonic grating, the computation time is significantly reduced to less than 10%, compared with the explicit cylindrical FDTD method.

This paper describes the design and implementation of a real-time optical flow processor using a single field-programmable gate array (FPGA) chip. By introducing the modified initial flow generation method, the successive over-relaxation (SOR) method for both layers, the optimization of the reciprocal operation method, and the image division method, it is now possible to both reduce hardware requirements and improve flow accuracy. Additionally, by introducing a pipeline structure to this processor, high-throughput hardware implementation could be achieved. Total logic cell (LC) amounts and processer memory capacity are reduced by about 8% and 16%, respectively, compared to our previous hierarchical optical flow estimation (HOE) processor. The results of our evaluation confirm that this processor can perform 30 fps wide extended graphics array (WXGA) 175.7MHz real-time optical flow processing with a single FPGA.