Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor

Yu SUZUKI; Masato ITO; Satoshi KANDA; Kousuke IMAMURA; Yoshio MATSUDA; Tetsuya MATSUMURA

doi:10.1587/transfun.E100.A.2888

Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor

Yu SUZUKI, Masato ITO, Satoshi KANDA, Kousuke IMAMURA, Yoshio MATSUDA, Tetsuya MATSUMURA

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This paper describes the design and implementation of a real-time optical flow processor using a single field-programmable gate array (FPGA) chip. By introducing the modified initial flow generation method, the successive over-relaxation (SOR) method for both layers, the optimization of the reciprocal operation method, and the image division method, it is now possible to both reduce hardware requirements and improve flow accuracy. Additionally, by introducing a pipeline structure to this processor, high-throughput hardware implementation could be achieved. Total logic cell (LC) amounts and processer memory capacity are reduced by about 8% and 16%, respectively, compared to our previous hierarchical optical flow estimation (HOE) processor. The results of our evaluation confirm that this processor can perform 30 fps wide extended graphics array (WXGA) 175.7MHz real-time optical flow processing with a single FPGA.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.12 pp.2888-2900

Publication Date: 2017/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E100.A.2888

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Authors

Yu SUZUKI
  Nihon University
Masato ITO
  Nihon University
Satoshi KANDA
  Nihon University
Kousuke IMAMURA
  Kanazawa University
Yoshio MATSUDA
  Kanazawa University
Tetsuya MATSUMURA
  Nihon University

Keyword

optical flow, HOE algorithm, SOR, FPGA, processor

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Yu SUZUKI, Masato ITO, Satoshi KANDA, Kousuke IMAMURA, Yoshio MATSUDA, Tetsuya MATSUMURA, "Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor" in IEICE TRANSACTIONS on Fundamentals, vol. E100-A, no. 12, pp. 2888-2900, December 2017, doi: 10.1587/transfun.E100.A.2888.
Abstract: This paper describes the design and implementation of a real-time optical flow processor using a single field-programmable gate array (FPGA) chip. By introducing the modified initial flow generation method, the successive over-relaxation (SOR) method for both layers, the optimization of the reciprocal operation method, and the image division method, it is now possible to both reduce hardware requirements and improve flow accuracy. Additionally, by introducing a pipeline structure to this processor, high-throughput hardware implementation could be achieved. Total logic cell (LC) amounts and processer memory capacity are reduced by about 8% and 16%, respectively, compared to our previous hierarchical optical flow estimation (HOE) processor. The results of our evaluation confirm that this processor can perform 30 fps wide extended graphics array (WXGA) 175.7MHz real-time optical flow processing with a single FPGA.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.2888/_p

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@ARTICLE{e100-a_12_2888,
author={Yu SUZUKI, Masato ITO, Satoshi KANDA, Kousuke IMAMURA, Yoshio MATSUDA, Tetsuya MATSUMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor},
year={2017},
volume={E100-A},
number={12},
pages={2888-2900},
abstract={This paper describes the design and implementation of a real-time optical flow processor using a single field-programmable gate array (FPGA) chip. By introducing the modified initial flow generation method, the successive over-relaxation (SOR) method for both layers, the optimization of the reciprocal operation method, and the image division method, it is now possible to both reduce hardware requirements and improve flow accuracy. Additionally, by introducing a pipeline structure to this processor, high-throughput hardware implementation could be achieved. Total logic cell (LC) amounts and processer memory capacity are reduced by about 8% and 16%, respectively, compared to our previous hierarchical optical flow estimation (HOE) processor. The results of our evaluation confirm that this processor can perform 30 fps wide extended graphics array (WXGA) 175.7MHz real-time optical flow processing with a single FPGA.},
keywords={},
doi={10.1587/transfun.E100.A.2888},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2888
EP - 2900
AU - Yu SUZUKI
AU - Masato ITO
AU - Satoshi KANDA
AU - Kousuke IMAMURA
AU - Yoshio MATSUDA
AU - Tetsuya MATSUMURA
PY - 2017
DO - 10.1587/transfun.E100.A.2888
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2017
AB - This paper describes the design and implementation of a real-time optical flow processor using a single field-programmable gate array (FPGA) chip. By introducing the modified initial flow generation method, the successive over-relaxation (SOR) method for both layers, the optimization of the reciprocal operation method, and the image division method, it is now possible to both reduce hardware requirements and improve flow accuracy. Additionally, by introducing a pipeline structure to this processor, high-throughput hardware implementation could be achieved. Total logic cell (LC) amounts and processer memory capacity are reduced by about 8% and 16%, respectively, compared to our previous hierarchical optical flow estimation (HOE) processor. The results of our evaluation confirm that this processor can perform 30 fps wide extended graphics array (WXGA) 175.7MHz real-time optical flow processing with a single FPGA.
ER -