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Norio KOIKE Hirokazu NISHIMURA Masato TAKEO Tomoyuki MORII Kenichiro TATSUUMA
Hot-carrier degradation of voltage controlled oscillator (VCO) was investigated by a reliability simulator known as BERT. The appropriate monitor of VCO frequency degradation shifts from the saturated drain current of an N MOSFET to linear drain current with an increase in VCO input voltage. The degradation of the VCO drastically increases with a small reduction in initial oscillation frequency. These results imply the need for an appropriate reliability margin around the standard operating point as well as a performance margin, which cannot be achieved by using conventional drain current monitors.
Koji ASARI Hiroshige HIRANO Toshiyuki HONDA Tatsumi SUMI Masato TAKEO Nobuyuki MORIWAKI George NAKANE Tetsuji NAKAKUMA Shigeo CHAYA Toshio MUKUNOKI Yuji JUDAI Masamichi AZUMA Yasuhiro SHIMADA Tatsuo OTSUKI
Ferroelectric non-volatile memory (FeRAM) has been inspiring interests since bismuth layer perovskite material family was found to provide "Fatigue Free" endurance, superior retention and imprint characteristics. In this paper, we will provide new circuits technology for FeRAM developed to implement high speed operation, low voltage operation and low power consumption. Performance of LSI embedded with FeRAM for contactless IC card is also provided to demonstrate the feasibility of the circuit technology.
Norio KOIKE Masato TAKEO Kenichiro TATSUUMA
A simulation methodology to analyze hot-carrier degradation due to bidirectional stressing in a static RAM circuit has been developed. The bidirectional stressing of pass transistors can approximate to unidirectional stressing. The effective stress direction of each NMOSFET can be determined by the higher of the two junction voltages at the peak substrate current generation. Aged SPICE parameter sets extracted in the forward or in the reverse mode are selected for simulating the degradation of each NMOSFET. Furthermore, effects of each NMOSFET degradation on the degraded circuit behavior are simulated. This technique helps detect an NMOSFET having the largest influence on the circuit aging, improving circuit reliability. The methodology was successfully applied to an SRAM device, and was validated by low temperature bias test data.