In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.

As LSIs are two-dimensional structures, the number of external pins increases at a lower rate than the corresponding increase in the number of gates on the LSI. Therefore, the number of flip-flops on a scan path increases as the density of gates on LSIs rises, resulting in longer test application times. In this paper, three novel DFT strategies aimed at reducing test application time are proposed. DFT strategy 1 is a full scan design method with test point insertion, DFT strategy 2 is a partial scan design method, and DFT strategy 3 is a partial scan design method with test point insertion. Experimental results show that these DFT strategies reduced the test application times by 45% to 82% compared with conventional full scan design methods.

In recent years, the growing density and complexity of VLSIs have led to an increase in the numbers of test patterns and fault models. Test patterns used in VLSI testing are required to provide high quality and low cost. Don't care (X) identification techniques and X-filling techniques are methods to satisfy these requirements. However, conventional X-identification techniques are less effective for application-specific fields such as test compaction because the X-bits concentrate on particular primary inputs and pseudo primary inputs. In this paper, we propose a don't care identification method for test compaction. The experimental results for ITC'99 and ISCAS'89 benchmark circuits show that a given test set can be efficiently compacted by the proposed method.

High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation in the capture cycle. Conventional low power dissipation oriented X-filling methods consecutively select FFs and assign values to decrease the number of transitions on the FFs. In this paper, we propose a novel low power dissipation oriented X-filling method using SAT Solvers that conducts simultaneous X-filling for some FFs. We also proposed a selection order of FFs based on a correlation coefficient between transitions of FFs and power dissipation. Experimental results show that the proposed method was effective for ISCAS'89 and ITC'99 benchmark circuits compared with justification-probability-based fill.