A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT

Masayoshi YOSHIMURA; Yoshiyasu TAKAHASHI; Hiroshi YAMAZAKI; Toshinori HOSOKAWA

doi:10.1587/transfun.E100.A.2824

A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT

Masayoshi YOSHIMURA, Yoshiyasu TAKAHASHI, Hiroshi YAMAZAKI, Toshinori HOSOKAWA

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High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation in the capture cycle. Conventional low power dissipation oriented X-filling methods consecutively select FFs and assign values to decrease the number of transitions on the FFs. In this paper, we propose a novel low power dissipation oriented X-filling method using SAT Solvers that conducts simultaneous X-filling for some FFs. We also proposed a selection order of FFs based on a correlation coefficient between transitions of FFs and power dissipation. Experimental results show that the proposed method was effective for ISCAS'89 and ITC'99 benchmark circuits compared with justification-probability-based fill.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.12 pp.2824-2833

Publication Date: 2017/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E100.A.2824

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Authors

Masayoshi YOSHIMURA
  Kyoto Sangyo University
Yoshiyasu TAKAHASHI
  Nihon University
Hiroshi YAMAZAKI
  Nihon University
Toshinori HOSOKAWA
  Nihon University

Keyword

transition faults, correlation, capture power reduction, X-filling, SAT

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Masayoshi YOSHIMURA, Yoshiyasu TAKAHASHI, Hiroshi YAMAZAKI, Toshinori HOSOKAWA, "A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT" in IEICE TRANSACTIONS on Fundamentals, vol. E100-A, no. 12, pp. 2824-2833, December 2017, doi: 10.1587/transfun.E100.A.2824.
Abstract: High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation in the capture cycle. Conventional low power dissipation oriented X-filling methods consecutively select FFs and assign values to decrease the number of transitions on the FFs. In this paper, we propose a novel low power dissipation oriented X-filling method using SAT Solvers that conducts simultaneous X-filling for some FFs. We also proposed a selection order of FFs based on a correlation coefficient between transitions of FFs and power dissipation. Experimental results show that the proposed method was effective for ISCAS'89 and ITC'99 benchmark circuits compared with justification-probability-based fill.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.2824/_p

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@ARTICLE{e100-a_12_2824,
author={Masayoshi YOSHIMURA, Yoshiyasu TAKAHASHI, Hiroshi YAMAZAKI, Toshinori HOSOKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT},
year={2017},
volume={E100-A},
number={12},
pages={2824-2833},
abstract={High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation in the capture cycle. Conventional low power dissipation oriented X-filling methods consecutively select FFs and assign values to decrease the number of transitions on the FFs. In this paper, we propose a novel low power dissipation oriented X-filling method using SAT Solvers that conducts simultaneous X-filling for some FFs. We also proposed a selection order of FFs based on a correlation coefficient between transitions of FFs and power dissipation. Experimental results show that the proposed method was effective for ISCAS'89 and ITC'99 benchmark circuits compared with justification-probability-based fill.},
keywords={},
doi={10.1587/transfun.E100.A.2824},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2824
EP - 2833
AU - Masayoshi YOSHIMURA
AU - Yoshiyasu TAKAHASHI
AU - Hiroshi YAMAZAKI
AU - Toshinori HOSOKAWA
PY - 2017
DO - 10.1587/transfun.E100.A.2824
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2017
AB - High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation in the capture cycle. Conventional low power dissipation oriented X-filling methods consecutively select FFs and assign values to decrease the number of transitions on the FFs. In this paper, we propose a novel low power dissipation oriented X-filling method using SAT Solvers that conducts simultaneous X-filling for some FFs. We also proposed a selection order of FFs based on a correlation coefficient between transitions of FFs and power dissipation. Experimental results show that the proposed method was effective for ISCAS'89 and ITC'99 benchmark circuits compared with justification-probability-based fill.
ER -