A MMIC power amplifier operating with a single-supply (3.0 V) has been developed for 5.8 GHz Japanese Electronic Toll Collection (ETC) System. The present MMIC contains two FETs, matching circuits (input, intermediate and output matching circuits), and two drain bias circuits. High dielectric constant material SrTiO3 (STO) is used for by-pass and input coupling capacitors. Very small die size of 0.77 mm2 has been realized by using the STO capacitors and negative feedback circuit technology. High 1 dB output gain compression point (P1dB) of 13 dBm, high gain of 21.4 dB and low dissipation current of 41.3 mA have been achieved under 3.0 V single-supply condition.

Highly miniaturization technology in front-end GaAs Hybrid IC for mobile communication equipment will be presented. A combination of MBB (micro bump bonding) technology and the new GaAs IC fabrication process using high dielectric constant (εr) thin film technology has achieved a super small HIC with low cost and low power consumption. The new HIC was constructed of only a ceramic substrate in which the spiral inductors were formed on it and the GaAs IC chip that was bonded by using MBB technology. The MBB technology lead the HIC to a lower temperature process without soldering, a smaller bump diameter, at shorter intervals and the lowest parasitic in the bump. The advantage of the small bonding pad of the IC contributes to miniaturize the IC chip and reduces the chip cost. The GaAs IC process technology using high-εr thin film achieves the integration of all capacitors in the IC without increasing the chip size. Furthermore, low power consumption was achieved by 0. 5-µm LDD BP-MESFET with a high k-value. Although capacitors were integrated on the IC, all of the inductors were formed on the top of the ceramic substrate using a thin film metal process. This was used due to its large occupation area when it was integrated on the IC, and produced a low Q-factor. As a results, the chip was minimized to a size of 0. 81. 0 mm2 and achieved a low-cost chip. Two types of HICs were fabricated for 880 MHz cellular band and 1. 9 GHz PHS (Personal Handy phone System) band. The HIC at 880 MHz measures only 5. 05. 01. 0 mm3, and offered a conversion gain of 25 dB, a noise figure of 4. 2 dB and an image rejection ratio of 12 dB at 2. 7 V and at a power supply of 3. 5 mA. The HIC for 1. 9 GHz measures only 3. 54. 01. 0 mm3, and showed a conversion gain of 16. 0 dB, a II P3 of -16. 0 dBm, and an image rejection ratio of over 20 dBc at 3. 0 V and at power supply of 4. 5 mA.

We report 0.15-µm T-shaped gate MODFETs using BCB (Benzocyclobutene) as low-k spacer dielectric material. The RF performance of pseudomorphic MODFET was improved by reducing the gate fringing capacitance using low-k material. The BCB film was deposited by plasma CVD technique at 100C and was patterned by lift-off technique. The dielectric constant of BCB film deposited by plasma CVD was confirmed 2.7, which is equal to that of spin-coated BCB, and is 35% lower than that of conventional SiO2. The leakage current was 4.710-5 A/cm2 at 3.6 MV/cm and was low enough for spacer material. 0.15-µm T-shaped gate MODFETs were fabricated by using BCB spacer and phase-shift lithography technique. More than 20 GHz increase of fmax was obtained in comparison with conventional SiO2 spacer by reducing the gate fringing capacitance.

Low-voltage technology in front-end GaAs IC for mobile communication equipment will be presented. New techniques in combination with different threshold voltage (Vth) FETs for an amplifier and a mixer were investigated for low-voltage operation of the IC. The amplifier and mixer consist of a cascode connected to FETs with shallow and deep Vth. The best suitable distribution of the supply voltages was accomplished for each FETs by using a combination of different Vth, and excellent RF characteristics of the IC were obtained, even at low voltage operation. In addition, this front-end IC has a high image rejection ratio (IRR) without using an external image rejection filter, but by using high Q-value input and intermediate matching circuits. The fabrication process used an asymmetric self-aligned BP-LDD process and high dielectric constant (high-εr) on-chip bypass capacitors using SrTiO3 contributed to a reduction in dissipation current, chip size and parasitic reactance in the source wires. The fabricated IC showed a conversion gain (CG) of 23 dB, noise figure (NF) of 2.8 dB, 3rd order output intercept point (IP3out) of 3 dBm, image rejection ratio (IRR) over 20 dBc and LO to RF isolation over 25 dB, operating by 1.0 V single supply with dissipation current of 6.8 mA at 880 MHz. At 1.9 GHz, the IC also showed excellent RF characteristics with dissipation current of 6.5 mA at 1.0 V. The IC die is very small the size is 0.75 mm0.75 mm, and is molded in a mini-6pin plastic package.