Highly miniaturization technology in front-end GaAs Hybrid IC for mobile communication equipment will be presented. A combination of MBB (micro bump bonding) technology and the new GaAs IC fabrication process using high dielectric constant (εr) thin film technology has achieved a super small HIC with low cost and low power consumption. The new HIC was constructed of only a ceramic substrate in which the spiral inductors were formed on it and the GaAs IC chip that was bonded by using MBB technology. The MBB technology lead the HIC to a lower temperature process without soldering, a smaller bump diameter, at shorter intervals and the lowest parasitic in the bump. The advantage of the small bonding pad of the IC contributes to miniaturize the IC chip and reduces the chip cost. The GaAs IC process technology using high-εr thin film achieves the integration of all capacitors in the IC without increasing the chip size. Furthermore, low power consumption was achieved by 0. 5-µm LDD BP-MESFET with a high k-value. Although capacitors were integrated on the IC, all of the inductors were formed on the top of the ceramic substrate using a thin film metal process. This was used due to its large occupation area when it was integrated on the IC, and produced a low Q-factor. As a results, the chip was minimized to a size of 0. 8
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Junji ITOH, Tadayoshi NAKATSUKA, Takayuki YOSHIDA, Mitsuru NISHITSUJI, Tomoya UDA, Osamu ISHIKAWA, "Miniaturized Front-End HIC Using MBB Technology for Mobile Communication Equipment" in IEICE TRANSACTIONS on Electronics,
vol. E81-C, no. 6, pp. 834-840, June 1998, doi: .
Abstract: Highly miniaturization technology in front-end GaAs Hybrid IC for mobile communication equipment will be presented. A combination of MBB (micro bump bonding) technology and the new GaAs IC fabrication process using high dielectric constant (εr) thin film technology has achieved a super small HIC with low cost and low power consumption. The new HIC was constructed of only a ceramic substrate in which the spiral inductors were formed on it and the GaAs IC chip that was bonded by using MBB technology. The MBB technology lead the HIC to a lower temperature process without soldering, a smaller bump diameter, at shorter intervals and the lowest parasitic in the bump. The advantage of the small bonding pad of the IC contributes to miniaturize the IC chip and reduces the chip cost. The GaAs IC process technology using high-εr thin film achieves the integration of all capacitors in the IC without increasing the chip size. Furthermore, low power consumption was achieved by 0. 5-µm LDD BP-MESFET with a high k-value. Although capacitors were integrated on the IC, all of the inductors were formed on the top of the ceramic substrate using a thin film metal process. This was used due to its large occupation area when it was integrated on the IC, and produced a low Q-factor. As a results, the chip was minimized to a size of 0. 8
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e81-c_6_834/_p
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@ARTICLE{e81-c_6_834,
author={Junji ITOH, Tadayoshi NAKATSUKA, Takayuki YOSHIDA, Mitsuru NISHITSUJI, Tomoya UDA, Osamu ISHIKAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Miniaturized Front-End HIC Using MBB Technology for Mobile Communication Equipment},
year={1998},
volume={E81-C},
number={6},
pages={834-840},
abstract={Highly miniaturization technology in front-end GaAs Hybrid IC for mobile communication equipment will be presented. A combination of MBB (micro bump bonding) technology and the new GaAs IC fabrication process using high dielectric constant (εr) thin film technology has achieved a super small HIC with low cost and low power consumption. The new HIC was constructed of only a ceramic substrate in which the spiral inductors were formed on it and the GaAs IC chip that was bonded by using MBB technology. The MBB technology lead the HIC to a lower temperature process without soldering, a smaller bump diameter, at shorter intervals and the lowest parasitic in the bump. The advantage of the small bonding pad of the IC contributes to miniaturize the IC chip and reduces the chip cost. The GaAs IC process technology using high-εr thin film achieves the integration of all capacitors in the IC without increasing the chip size. Furthermore, low power consumption was achieved by 0. 5-µm LDD BP-MESFET with a high k-value. Although capacitors were integrated on the IC, all of the inductors were formed on the top of the ceramic substrate using a thin film metal process. This was used due to its large occupation area when it was integrated on the IC, and produced a low Q-factor. As a results, the chip was minimized to a size of 0. 8
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Miniaturized Front-End HIC Using MBB Technology for Mobile Communication Equipment
T2 - IEICE TRANSACTIONS on Electronics
SP - 834
EP - 840
AU - Junji ITOH
AU - Tadayoshi NAKATSUKA
AU - Takayuki YOSHIDA
AU - Mitsuru NISHITSUJI
AU - Tomoya UDA
AU - Osamu ISHIKAWA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1998
AB - Highly miniaturization technology in front-end GaAs Hybrid IC for mobile communication equipment will be presented. A combination of MBB (micro bump bonding) technology and the new GaAs IC fabrication process using high dielectric constant (εr) thin film technology has achieved a super small HIC with low cost and low power consumption. The new HIC was constructed of only a ceramic substrate in which the spiral inductors were formed on it and the GaAs IC chip that was bonded by using MBB technology. The MBB technology lead the HIC to a lower temperature process without soldering, a smaller bump diameter, at shorter intervals and the lowest parasitic in the bump. The advantage of the small bonding pad of the IC contributes to miniaturize the IC chip and reduces the chip cost. The GaAs IC process technology using high-εr thin film achieves the integration of all capacitors in the IC without increasing the chip size. Furthermore, low power consumption was achieved by 0. 5-µm LDD BP-MESFET with a high k-value. Although capacitors were integrated on the IC, all of the inductors were formed on the top of the ceramic substrate using a thin film metal process. This was used due to its large occupation area when it was integrated on the IC, and produced a low Q-factor. As a results, the chip was minimized to a size of 0. 8
ER -