A 60 GHz direct conversion transceiver which employs amplitude/phase imbalance cancellation technique is newly proposed. By using the proposed technique, the receive path of the transceiver achieves less than 0.2 dB of amplitude error and less than 3 of phase error at 60 GHz bands over a 10 GHz bandwidth, which relaxes the design accuracy required for baluns used in the transceiver. It also employs a simple and fast calibration algorithm to adjust the locking range of the divide-by-3 injection locked divider in the phase locked loop. Fabricated in 90 nm CMOS technology, the transceiver achieves a low power consumption of 230 mW in transmit mode and 173 mW in receive mode. The output spectrum of 1.76 Gsps π/2-BPSK/QPSK modulation shows the excellent distortion and spurious suppression that meet the IEEE802.11ad draft standard.

This paper presents a 60 GHz analog/digital beamforming receiver that effectively suppresses interference signals, targeting the IEEE 802.11ad/WiGig standard. Combining two-stream analog frontends with interference rejection digital signal processing, the analog beamforming steers the antenna beam to the desired direction while the digital beamforming provides gain suppression in the interference direction. A prototype has been built with 40 nm CMOS analog frontends as well as offline baseband digital signal processing. Measurements show a 3.1 dB EVM advantage over conventional two-stream diversity during a packet collision situation.

The Direct Sampling Mixer (DSM) with a complex coefficient transfer function is demonstrated. The operation theory and the detail design methodology are discussed for the high order complex DSM, which can achieve large image rejection ratio by introducing the attenuation pole at the image frequency band. The proposed architecture was fabricated in a 65 nm CMOS process. The measured results agree well with the theoretical calculation, which proves the validity of the proposed architecture and the design methodology. By using the proposed design method, it will be possible for circuit designers to design the DSM with large image rejection ratio without repeated lengthy simulations.

This paper presents an automatic gain control (AGC) system suitable for 60GHz direct conversion receivers. By using a two step gain control algorithm with high-pass filter cutoff frequency switching, the proposed AGC system realizes fast settling time and wide dynamic range simultaneously. The paper also discusses wide-bandwidth variable gain amplifier (VGA) design. By introducing digitally-controlled resistors and gain flattening capacitors, the proposed VGA realizes wide gain range while compensating gain variations due to parasitic capacitance of MOS switches. The AGC system is implemented in a transceiver chipset where RFIC and BBIC are fabricated in 90nm CMOS and 40nm CMOS respectively. The measurement shows excellent dynamic range of 47dB with +/-1dB gain accuracy within 1µs settling time, which satisfies the stringent requirements of the IEEE802.11ad standard.

This paper presents a wideband digital predistortion (DPD) architecture suitable for wideband wireless systems, such as IEEE 802.11ad/WiGig, where low oversampling ratio of the digital-to-analog converter (DAC) is a bottleneck for available linearization bandwidth. In order to overcome the bandwidth limitation in the conventional DPD, the proposed DPD introduces a complex coefficient filter in the DPD signal processing, which enables it to achieve asymmetric linearization. This approach effectively suppresses one side of adjacent channel leakages with twice the bandwidth as compared to the conventional DPD. The concept is verified through system simulation and measurements. Using a scaled model of a 2 GHz RF carrier frequency, the measurement shows a 4.2 dB advantage over the conventional DPD in terms of adjacent channel leakage.