This paper shows activities of the ultra wideband (UWB) research and development consortium organized by the National Institute of Information and Communications Technology (NICT). Fully CMOS monolithic microwave integrate circuits (MMICs) are designed and fabricated both for the multiband OFDM and the impulse radio. UWB transceivers are constructed with the MMICs as their front-end devices and evaluated by some measurements such as time domain waveform, spectrum, error vector magnitude, and so on. To show the application capabilities of the UWB transceivers, two kinds of video transmission system are constructed and demonstrated.

This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65 nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34 GHz with reference signals of 528 MHz was -119 dBc/Hz.

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (Dll) for deskew, and a frequency-locked loop(FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector newly developed which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4µm CMOS technology is used to fabricate the chip.

A low VDD current mirror with deep sub-micron vertical MOSFETs is presented. The keys are new bias circuits to reduce both the minimum VDD for the operation and the sensitivity of the output current on VDD. In the simulation, our circuits reduce the minimum VDD by about 17% and the VDD sensitivity by one order both from those of the conventional. In the simulation with 90nm φ vertical MOSFET approximate models, our circuit shows about 4MΩ output resistance at 1.2-V VDD with the small temperature dependence, which is about six times as large as that with planar MOSFETs.