A Monolithic amplifier IC with small phase deviation applying parallel feed back technique was developed by using high speed Si bipolar process technology. This IC achieves a phase deviation of 1.8, an S21 gain of 46 dB and a limiting output of 7.8 dBm at 1 GHz.

This paper describes design techniques for suppressing crosstalk in an optical transceiver module using PLC-hybrid-integration technologies and for achieving burst-mode operation with high sensitivity and wide dynamic range using CMOS-IC technologies. An arrangement that reduces the electrical crosstalk to less than -100 dB was designed using three-dimensional electromagnetic field analysis. The configurations of a newly developed instantaneous-response CMOS LD driver circuit is also described and instantaneous-response CMOS receiver circuit techniques are reviewed. With these techniques, we have succeeded in building optical transceiver modules for ATM-PON systems using PLC-hybrid-integration and inexpensive standard CMOS-IC fabrication processes. Under full-duplex operation at 156 Mb/s, fabricated transceiver modules showed receiver sensitivity of better than -34 dBm and dynamic range of over 28 dB, which satisfy both the class-B and class-C specifications recommended by ITU-T (International Telecommunication Union-Telecommunication standardization sector) G983.1 for the optical transceiver module for an ONU (optical network unit).

A high-gain wide-band amplifier IC module is needed for high-speed communication systems. However, it is difficult to expand bandwidth and maintain stability. This is because small parasitic influences, such as bonding-wire inductance or the capacitance of the package, become large at high frequencies, thus degrading performance or causing parasitic oscillation. In this paper, a new design procedure is proposed for the high-gain and wide-band IC module, using stability analysis and a unified design methodology for IC's and packages. A multichip structure is developed using stability analysis and the requirements for stable operation are determined for each IC chip, package, and interface condition between them. Furthermore, to reduce the parasitic influences, several improvements in the interface and package design are clarified, such as wide-band matching and LC resonance damping. IC design using effective feedback techniques for enlarging the bandwidth are also presented. The IC's are fabricated using 0.2-µm GaAs MESFET IC technology. To verify the validity of these techniques, an equalizer IC module for 10-Gb/s optical communication systems was fabricated achieving a gain of 36 dB and a bandwidth of 9 GHz.

This paper describes design techniques for suppressing crosstalk in an optical transceiver module using PLC-hybrid-integration technologies and for achieving burst-mode operation with high sensitivity and wide dynamic range using CMOS-IC technologies. An arrangement that reduces the electrical crosstalk to less than -100 dB was designed using three-dimensional electromagnetic field analysis. The configurations of a newly developed instantaneous-response CMOS LD driver circuit is also described and instantaneous-response CMOS receiver circuit techniques are reviewed. With these techniques, we have succeeded in building optical transceiver modules for ATM-PON systems using PLC-hybrid-integration and inexpensive standard CMOS-IC fabrication processes. Under full-duplex operation at 156 Mb/s, fabricated transceiver modules showed receiver sensitivity of better than -34 dBm and dynamic range of over 28 dB, which satisfy both the class-B and class-C specifications recommended by ITU-T (International Telecommunication Union-Telecommunication standardization sector) G983.1 for the optical transceiver module for an ONU (optical network unit).

This paper describes techniques for widening lock and pull-in ranges and suppressing jitter in clock and data recovery ICs. It is shown theoretically that using a duplicated loop control (DLC)-phase-locked loop (PLL) technique enables wider lock and pull-in ranges in clock and data recovery (CDR) without increasing the cut-off frequency of the jitter transfer function. A 2.5-Gb/s DLC-CDR IC fabricated with a 0.5-µm Si bipolar process provides 2.5 times the lock range and 1.5 times the pull-in range of a conventional CDR IC, and the jitter characteristics of the fabricated CDR IC meet all three STM-16 jitter specifications in ITU-T recommendation G.958.

We fabricated a 1.55-µm polarization insensitive Michelson interferometric wavelength converter (MI-WC). The MI-WC consists of a two-channel spot-size converter integrated semiconductor optical amplifier (SS-SOA) on a planar lightwave circuit (PLC) platform. Clear eye opening and no power penalty in the back-to-back condition were obtained at 10 Gb/s modulation. We also confirmed the polarization insensitive operation on the input signal. Moreover, for an application of the MI-WC to DWDM networks, we demonstrated the selective wavelength conversion of 2.5 G/s optical packets from Fabry-Perot laser diode (FP-LD) light to four ITU-T grid wavelengths. We confirmed the good feasibility of this technique for use in DWDM networks. The wavelength conversion we describe here is indispensable for future all-optical networks, in which optical signal sources without wavelength control will be used at user-end terminals.

We fabricated a 1.55-µm polarization insensitive Michelson interferometric wavelength converter (MI-WC). The MI-WC consists of a two-channel spot-size converter integrated semiconductor optical amplifier (SS-SOA) on a planar lightwave circuit (PLC) platform. Clear eye opening and no power penalty in the back-to-back condition were obtained at 10 Gb/s modulation. We also confirmed the polarization insensitive operation on the input signal. Moreover, for an application of the MI-WC to DWDM networks, we demonstrated the selective wavelength conversion of 2.5 G/s optical packets from Fabry-Perot laser diode (FP-LD) light to four ITU-T grid wavelengths. We confirmed the good feasibility of this technique for use in DWDM networks. The wavelength conversion we describe here is indispensable for future all-optical networks, in which optical signal sources without wavelength control will be used at user-end terminals.

This paper describes a new timing circuit design technique for asynchronous burst-mode data transmission such as Fiber-To-The-Home (FTTH). It enables to the handling of asynchronous burst-mode data. Without an external reference clock signal, it can make a quick extraction of clock signal from received data packets using a "gating-timing circuit" and a "burst PLL." The gating-timing circuit employs bit gating for a quick phase response, and the burst PLL employs frame gating for quick frequency adjustment to differences between packets and clock extraction. This circuit has a simple configuration without any external oscillators, which reduces both cost and power. A fabricated 0.5-µm CMOS IC exhibits instantaneous response within one bit for 156 Mb/s asynchronous data packets.

As great advancements have been made in CMOS process technology over the past 20 years, RF CMOS circuits operating in the microwave band have rapidly developed from component circuit levels to multiband/multimode transceiver levels. In the next ten years, it is highly likely that the following devices will be realized: (i) versatile transceivers such as those used in software-defined radios (SDR), cognitive radios (CR), and reconfigurable radios (RR); (ii) systems that operate in the millimeter-wave or terahertz-wave region and achieve high speed and large-capacity data transmission; and (iii) microminiaturized low-power RF communication systems that will be extensively used in our everyday lives. However, classical technology for designing analog RF circuits cannot be used to design circuits for the abovementioned devices since it can be applied only in the case of continuous voltage and continuous time signals; therefore, it is necessary to integrate the design of high-speed digital circuits, which is based on the use of discrete voltages and the discrete time domain, with analog design, in order to both achieve wideband operation and compensate for signal distortions as well as variations in process, power supply voltage, and temperature. Moreover, as it is thought that small integration of the antenna and the interface circuit is indispensable to achieve miniaturized micro RF communication systems, the construction of the integrated design environment with the Micro Electro Mechanical Systems (MEMS) device etc. of the different kind devices becomes more important. In this paper, the history and the current status of the development of RF CMOS circuits are reviewed, and the future status of RF CMOS circuits is predicted.

This paper describes the technological issues in achieving a low-cost hybrid WDM module for access network systems. The problems which should be resolved in developing a low-cost module are clarified from the viewpoint of the module assembly in mass production. A design concept for a low-cost module suitable for mass production is indicated, which simplifies the alignment between a laser diode and a waveguide, and reduces the number of the components such as lenses and mirrors. The low-cost module is achieved by employing a flip-chip bonding method with passive alignment using a spot-size converter integrated laser diode (SS-LD) and p-i-n waveguide photodiodes (WGPDs) on a planar lightwave circuit (PLC) platform. We confirm that the SS-LD and the WGPD provide high coupling efficiency with a large tolerance for passive alignment. To achieve a high-sensitivity receiver, the module is designed to employ an asymmetric PLC Y-splitter that prefers a PD responsivity to an LD output power because of the high-coupling efficiency of the LD, and to employ a bare preamplifier mounting to reduce the parasitic capacitance into a preamplifier. We also demonstrate the dynamic performance for a 50-Mb/s burst signal, such as a high sensitivity, an instantaneous AGC response, and a small APC deviation of the transceiver.

This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65 nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34 GHz with reference signals of 528 MHz was -119 dBc/Hz.

This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.

One of the interesting submicron MOS FET characteristics is the effect of carrier velocity saturation (CVS) on the drain current. In the CVS region, the transconductance becomes constant independent both of the gate and the drain voltage. In this paper, RF MOS amplifier design technique using the CVS region has been proposed. By setting the FET gate bias to the power supply voltage Vdd, stable operation against Vdd variations can be achieved with a simple circuit configuration. By using this, a 5 GHz amplifier has been designed and fabricated by using 0.18-µm CMOS process technology. The chip has been operated with a gain variation less than 1 dB having a peak gain of 13.5 dB from 1.2 to 2.9 V Vdd.

This paper describes a 2.5-Gb/s optical receiver and transmitter chipset consisting of a preamplifier, a main amplifier, a clock and data recovery (CDR) circuit, and a laser-diode (LD) driver. Low-voltage and adjustment-free circuit techniques are introduced in order to achieve low cost and low power circuits. Circuit adjustments are eliminated by using a multi-stage automatic offset canceling technique in the main amplifier, and by using a PLL structure with a sample-and-hold technique in the CDR circuit. For power reduction, ICs are operated at a power supply voltage of -3 V. Fabricating the ICs by a 0.5-µm Si bipolar process makes it possible to achieve 2.5-Gb/s receiver and transmitter operation with a total power dissipation of 1.04 W. Especially significant is that the receiver ICs need no external devices and adjustments.

A wireless sensor terminal module of 5cc size (2.5 cm × 2.5 cm × 0.8 cm) that does not require a battery is proposed by integrating three kinds of circuit technologies. (i) a low-power sensor interface: an FM modulation type CMOS sensor interface circuit that can operate with a typical power consumption of 24.5 μW was fabricated by the 0.7-μm CMOS process technology. (ii) power supply to the sensor interface circuit: a wireless power transmission characteristic to a small-sized PCB spiral coil antenna was clarified and applied to the module. (iii) wireless sensing from the module: backscatter communication technology that modulates the signal from the base terminal equipment with sensor information and reflects it, which is used for the low-power sensing operation. The module fabricated includes a rectifier circuit with the PCB spiral coil antenna that receives wireless power transmitted from base terminal equipment by electromagnetic resonance coupling and converts it into DC power and a sensor interface circuit that operates using the power. The interface circuit modulates the received signal with the sensor information and reflects it back to the base terminal. The module could achieve 100 mm communication distance when 0.4 mW power is feeding to the sensor terminal.