A rack-mounted prototype packet switch that makes use of wavelength-division-multiplexing (WDM) interconnect techniques has been developed. The switch has a maximum throughput of 320 Gbit/s. It features a WDM star-based switch architecture, an electrical control circuit layer and a broad-bandwidth optical WDM layer. The basic characteristics of the broad bandwidth WDM layer, such as level diagram, transmission characteristics, 32-wavelength-channel switching, and high-speed optical gating within a 1.6-ns guard time, are described. Experimental results demonstrated that the switch can perform practical self-routing switch operations, such as address-extraction, optical buffering, and filtering for packet speeds of up to 10 Gbit/s. The switch is promising for such applications as a terabit-per-second switching node in future WDM transport networks.

The switch LSI described here takes advantage of the special characteristics of fully-depleted CMOS/SIMOX devicesthat is, source/drain capacitances and threshold voltages that are lower than those of conventional bulk CMOS devicesto boost the I/O bit rate. The double-edge triggered MUX/DEMUX which uses a frame synchronization logic, and the active-pull-up I/O provide a 144-pin, 2. 5-Gbps/pin interface on the chip. The 220-kgate rerouting banyan switching network with 110-kbit RAM operates at an internal clock frequency of 312 MHz. The CMOS/SIMOX LSI consumes 8. 4 W when operating with a 2-V power supply, and has four times the throughput of conventional one-chip ATM switch LSIs.

This paper describes the design and evaluation of a high-performance multicast ATM switch and its feasibility study, including its 40 Gbit/s LSI packaging. The multicast switch is constructed using a serial combination of rerouting networks and employs an adapted Boolean interval-splitting scheme for a generalized self-routing algorithm. Analysis and computer simulation results show that the cell loss probability is easily controlled by increasing the number of switching stages. It is shown that the switch configuration can be transformed into other patterns to be built from banyan-based subnetworks of arbitrary size for LSI packaging. It is also shown that an LSI chip integrating an 88 banyan-based subnetwork using 0. 25-µm CMOS/SIMOX technology can attain a 40-Gbit/s switching capability.

LSI chips were developed that fit on a switching fabric using chip-to-chip optical interconnections; they have 10-Gb/s serial input and output ports, which facilitates the layout of optically interfaced switching element modules. A test switching modeule composed of these chips was operated at 10.2 Gb/s without bit errors. Ultrahigh-speed switching LSI chips have been developed for a future asynchronous transfer mode (ATM) switching system with an over-Tb/s capacity. Their serial input and output ports facilitate chip-to-chip optical interconnection. Cell-dropper and crosspoint-router LSI chips, composing the core of the switching element, were fabricated by using GaAs LSI technology. A test switching module composed of these chips was operated at 10.2 Gb/s without bit errors.