This paper describes a new active pull-up (APU) interface for high-speed point-to-point transmission. The APU circuit is used to speed up a low-power-consumption open-drain-type interface. It pulls up the output at a fixed duration and this limiting of the pull-up duration prevents the pull-up operation from going into a counter phase at over 1-Gbps operation. Measurements of test chips fabricated with 0.25-µm bulk CMOS show. 1.7-Gbps error-free operation for the APU interface and 1.2-Gbps operation for the open-drain-type interface: The APU interface is 1.4 faster than the open-drain type. The application of a 0.25-µm SIMOX-CMOS device to the APU interface increases the bit rate 1.5 times compared with 0.25-µm bulk CMOS. Altogether the interface covers the bit rate of 2.4 Gbps, which is a layer of the communication hierarchy. The APU interface circuit can be applied to large-pin-count LSIs because of its full-CMOS single-rail structure.

A new low-power and high-speed CMOS interface circuit is proposed in which signals are transmitted by means of impulse voltage. This mode of transmission is called impulse transmission. Although a termination resistor is used for impedance matching, the current through the output transistors and the termination resistor flows only in transient states and no current flows in stable states. The output buffer and the termination resistor dissipate power only in transient states, so their power dissipation is reduced to 30% that of conventional low-voltage-swing CMOS interface circuits at 160 MHz. The circuit was fabricated by 0.5 µm CMOS technology and was evaluated at a supply voltage of 3.3 V. Experimental results confirm low power of 4.8 mW at 160 MHz and high-speed 870 Mb/s error free point-to-point transmission.

A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10 Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect level-varying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-µm CMOS process. It successfully operates at a data rate of 10.3125 Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2 ns with AC-coupling without a reset signal. The IC also demonstrates 1001 bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.

The switch LSI described here takes advantage of the special characteristics of fully-depleted CMOS/SIMOX devicesthat is, source/drain capacitances and threshold voltages that are lower than those of conventional bulk CMOS devicesto boost the I/O bit rate. The double-edge triggered MUX/DEMUX which uses a frame synchronization logic, and the active-pull-up I/O provide a 144-pin, 2. 5-Gbps/pin interface on the chip. The 220-kgate rerouting banyan switching network with 110-kbit RAM operates at an internal clock frequency of 312 MHz. The CMOS/SIMOX LSI consumes 8. 4 W when operating with a 2-V power supply, and has four times the throughput of conventional one-chip ATM switch LSIs.

This paper proposes an on-chip loop gain variation compensation architecture for a clock and data recovery (CDR) LSI. The CDR LSI using the proposed architecture can meet the jitter specifications recommended in ITU-T G.958 under wide variation of temperature and supply voltage. The relation between the jitter specifications and the loop gain is derived theoretically. Gain-variation characteristics of component circuits are studied by circuit simulation. The proposed architecture uses voltage controllers to reduce the gain variation of the LC voltage controlled oscillator (LC-VCO) circuit and charge-pump circuit. The voltage controllers are designed to have a first-order positive coefficient to temperature, which is found by an analysis of the gain variation characteristics. An STM-16 CDR with the proposed architecture is implemented in 0.20-µm fully depleted CMOS/SOI. The CDR shows a wide capture range of 140 MHz and meets both the jitter transfer and the jitter tolerance specifications in the ambient temperature range from -40 to 85 and with the supply voltage variation of 6%.

The 10-gigabit Ethernet passive optical network (10G-EPON) is a promising candidate for the next generation of fiber-to-the-home access systems. In the symmetric 10G-EPON system, the gigabit Ethernet passive optical network (GE-PON) and 10G-EPON will have to co-exist on the same optical network. For this purpose, an optical triplexer (10G-transmitter, 1G-transmitter, and 10G/1G-receiver) for optical line terminal (OLT) transceivers in 10G/1G co-existing EPON systems has been developed. Reducing the size and cost of the optical triplexer has been one of the largest issues in the effort to deploy 10G-EPON systems for practical use. In this paper, we describe a novel small and low-cost dual-rate optical triplexer for use in 10G-EPON applications. By reducing the optical path length by means of a light collection system with a low-magnification long-focus coupling lens, we have successfully miniaturized the optical triplexer for use in 10G-EPON OLT 10-gigabit small form factor pluggable (XFP) transceivers and decreased the number of lenses. A low-cost design of sub-assemblies also contributes to cost reduction. The triplexer's performance complies with IEEE 802.3av specifications.