The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the high-speed multilevel reading with a wider current sensing margin and the high-speed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed.

A novel design for temperature-compensated complementary metal-oxide semiconductor (CMOS) voltage reference sources by using the 1st order voltage reference taking into account the electrical property of the conventional current generator was proposed to minimize a temperature coefficient. A temperature coefficient of the proposed voltage reference source was estimated by using the current generator, which operated at smaller or larger temperature in comparison with the optimized operating temperature. The temperature coefficient at temperature range between -40 and 125, obtained from the simulated data by using hynix 0.35 µm CMOS technology, was 3.33 ppm/. The simulated results indicate that the proposed temperature-compensated CMOS voltage reference sources by using the 1st order voltage reference taking into account the electrical properties of the conventional current generator can be used to decrease the temperature coefficient.

The programming characteristics of polysilicon-aluminum oxide-nitride-oxide-silicon (SANOS) nonvolatile memory devices with Al2O3 and SiO2 stacked tunneling layers were investigated. The electron and hole drifts in the Si3N4 layer were calculated to determine the program speed of the proposed SANOS devices. Simulation results showed that enhancement of the programming speed in SANOS was achieved by utilizing SiO2 and Al2O3 stacked tunneling layers.