This paper describes, for the first time, an experimental study on the layout design considerations of GaAs HBT MMIC switchable-amplifier-chain-based power amplifiers (SWPAs) for CDMA handsets. The transient response of the quiescent current and output power (Pout) in GaAs HBT power amplifiers that consist of a main chain and a sub-chain is often affected by a thermal coupling between power stages and their bias circuits in the same chain or a thermal coupling between power stages and/or their bias circuits in different chains. In particular, excessively strong thermal coupling inside the MMIC SWPA causes failure in 3GPP-compliant inner loop power control tests. An experimental study reveals that both the preheating in the main/sub-chains and appropriate thermal coupling inside the main chain are very effective in reducing the turn-on delay for the two-parallel-amplifier-chain topology; for example, i) the sub-power stage is arranged near the main power stage, ii) the sub-driver stage is placed near the main driver stage and iii) the main driver bias circuit is placed near the main power stage and the sub-power stage. The SWPA operating in Band 9 (1749.9 to 1784.9 MHz), which was designed and fabricated from the foregoing considerations, shows a remarkable improvement in the Pout turn-on delay: a reduced power level error of 0.74 dB from turn-off to turn-on in the sub-amplifier chain and a reduced power level error of over 0.30 dB from turn-off to turn-on in the main amplifier chain. The main RF power measurements conducted with a 3.4-V supply voltage and a Band 9 WCDMA HSDPA modulated signal are as follows. The SWPA delivers a Pout of 28.5 dBm, a power gain (Gp) of 28 dB, and a PAE of 39% while restricting the ACLR1 to less than -40 dBc in the main amplifier chain. In the sub-amplifier chain, 17 dBm of Pout, 23.5 dB of Gp, and 27% of PAE are obtained at the same ACLR1 level.

This paper describes, for the first time, the circuit design considerations and measurements of core building blocks that support a 1.9-GHz-band (Band I) BiFET MMIC three-power-mode power amplifier (PA) for WCDMA handset applications. The blocks are a reference voltage (Vref) generator, a control logic circuit, and ESD protection circuits. Our proposed Vref-generator, based on a current-mirror topology, can successfully suppress Vref variation against threshold voltage (Vth) dispersion in the FET as well as current gain dispersion in the HBT. On-wafer measurements over several wafer lots show that the standard deviation of Vref is as small as 18 mV over a Vth dispersion range from -0.6 V to -1.0 V. As a result, the measured quiescent current dispersion in the HPM is also suppressed to less than 5.4 mA, despite the fact that the average quiescent current is relatively high, at 81.3 mA. Several simulations reveal that small decoupling capacitances of approximately 1 pF added to the gate control lines of RF switch FETs ensure stable operation of the control logic even if an undesired RF coupling is present between an RF signal path and the gate lines. An empirical and useful design approach for ESD protection using HBT base-collector diodes allows easy and precise estimation of the HBM ESD robustness. With the above building blocks, a 3 mm × 3 mm PA was designed and fabricated by an in-house BiFET process. Measurements conducted under the conditions of a 3.4-V supply voltage and a 1.95-GHz WCDMA modulated signal are as follows. The PA delivers a 28.3-dBm output power (Pout), a 28.2-dB power gain (Gp), and 40% PAE while restricting the ACLR1 to less than -42 dBc in the HPM. In the MPM, 17.4 dBm of Pout, 15.9 dB of Gp, and 25.3% of PAE are obtained, while in the LPM, the PA delivers 7 dBm of Pout, 11.7 dB of Gp, and 13.9% of PAE. The HBM ESD robustness is 2 kV.

This paper describes 0.8-/1.5-GHz-band GaAs-HBT power amplifier modules with a newly designed analog bias control scheme. This scheme has two features. One is to achieve approximately linear quiescent current control using not a BiFET process but only the usual HBT process. The other is to help improve linearity under reduced supply voltage and lower quiescent current operation. The following two key techniques are incorporated into the bias scheme. The first is to employ two different kinds of bias circuits: emitter follower bias and current injection bias. The second is the unique current injection bias block, based on the successful combination of an input buffer with an emitter resistance load and a current mirror. These techniques allow quiescent current control that is almost proportional to an externally applied analog control voltage. To confirm the effectiveness of the scheme, 0.8-GHz-band and 1.5-GHz-band power amplifier modules were designed and fabricated using the usual HBT process. Measurements conducted under the conditions of a 3.4V supply voltage and an HSDPA WCDMA modulated signal are as follows. The 0.8-GHz-band amplifier can deliver a 28-dBm output power (Pout), a 28.4-dB power gain (Gp), and 42% PAE while restricting the ACLR to less than -40dBc. For the 1.5-GHz-band amplifier, 28dBm of Pout, 29dB of Gp, and 41% of PAE are obtained with the same ACLR levels. The measurements also confirm that the quiescent current for the second stage in the amplifiers is approximately linearly changed from 14mA to 58mA over a control voltage ranging from 1.1V to 2.2V. In addition, our measured DG.09-based current dissipation with both supply voltage and analog bias controls is as low as 16.9mA, showing that the analog bias control scheme enables an average current reduction of more than 20%, as compared to a conventional supply voltage and two-step quiescent current control.