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Tomoko MATSUMOTO Yasuyuki HATAKAWA Satoshi KONISHI
This paper proposes an open loop beamforming scheme for downlink multiuser multiple-input multiple-output (MIMO) transmissions in frequency division duplex (FDD). The proposed scheme uses the uplink direction of arrival (DOA) estimation, and then generates the beamforming weight such that the interference caused by the overlapping beams is removed by applying the dirty-paper coding (DPC) principle. The simulation results show that the proposed scheme provides the gain of 32.3% at minimum in terms of the spectral efficiency at the CDF of 50% compared to the conventional DOA based beamforming scheme. In addition, it is shown that the proposed scheme has superior performance to closed loop scheme with the limited feedback information.
This letter proposes a simple combined coding and modulation based on super-orthogonal convolutional codes (SOCs) in order to support both coherent and non-coherent ultra-wideband (UWB) receivers. In the proposed scheme, the coherent receivers obtain a coding gain as large as the SOC while simultaneously supporting non-coherent receivers. In addition, their performance can be freely adapted by changing the encoder constraint length and the number of PPM slots according to its application. Thus, the proposal enables a more flexible system design for low data-rate UWB systems.
Kosuke SHIMAZAKI Shingo YOSHIZAWA Yasuyuki HATAKAWA Tomoko MATSUMOTO Satoshi KONISHI Yoshikazu MIYANAGA
This paper presents a VLSI design of a Tomlinson-Harashima (TH) precoder for multi-user MIMO (MU-MIMO) systems. The TH precoder consists of LQ decomposition (LQD), interference cancellation (IC), and weight coefficient multiplication (WCM) units. The LQ decomposition unit is based on an application specific instruction-set processor (ASIP) architecture with floating-point arithmetic for high accuracy operations. In the IC and WCM units with fixed-point arithmetic, the proposed architecture uses an arrayed pipeline structure to shorten a circuit critical path delay. The implementation result shows that the proposed architecture reduces circuit area and power consumption by 11% and 15%, respectively.