A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing

Kosuke SHIMAZAKI; Shingo YOSHIZAWA; Yasuyuki HATAKAWA; Tomoko MATSUMOTO; Satoshi KONISHI; Yoshikazu MIYANAGA

doi:10.1587/transfun.E96.A.2114

A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing

Kosuke SHIMAZAKI, Shingo YOSHIZAWA, Yasuyuki HATAKAWA, Tomoko MATSUMOTO, Satoshi KONISHI, Yoshikazu MIYANAGA

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This paper presents a VLSI design of a Tomlinson-Harashima (TH) precoder for multi-user MIMO (MU-MIMO) systems. The TH precoder consists of LQ decomposition (LQD), interference cancellation (IC), and weight coefficient multiplication (WCM) units. The LQ decomposition unit is based on an application specific instruction-set processor (ASIP) architecture with floating-point arithmetic for high accuracy operations. In the IC and WCM units with fixed-point arithmetic, the proposed architecture uses an arrayed pipeline structure to shorten a circuit critical path delay. The implementation result shows that the proposed architecture reduces circuit area and power consumption by 11% and 15%, respectively.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.11 pp.2114-2119

Publication Date: 2013/11/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E96.A.2114

Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)

Category: VLSI Design Technology and CAD

Authors

Kosuke SHIMAZAKI
  Hokkaido University
Shingo YOSHIZAWA
  Kitami Institute of Technology
Yasuyuki HATAKAWA
  KDDI R&D Laboratories Inc.
Tomoko MATSUMOTO
  KDDI R&D Laboratories Inc.
Satoshi KONISHI
  KDDI R&D Laboratories Inc.
Yoshikazu MIYANAGA
  Hokkaido University

Keyword

multi-user MIMO, Tomlinson-Harashima precoding, LQ decomposition, interference cancellation

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Kosuke SHIMAZAKI, Shingo YOSHIZAWA, Yasuyuki HATAKAWA, Tomoko MATSUMOTO, Satoshi KONISHI, Yoshikazu MIYANAGA, "A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing" in IEICE TRANSACTIONS on Fundamentals, vol. E96-A, no. 11, pp. 2114-2119, November 2013, doi: 10.1587/transfun.E96.A.2114.
Abstract: This paper presents a VLSI design of a Tomlinson-Harashima (TH) precoder for multi-user MIMO (MU-MIMO) systems. The TH precoder consists of LQ decomposition (LQD), interference cancellation (IC), and weight coefficient multiplication (WCM) units. The LQ decomposition unit is based on an application specific instruction-set processor (ASIP) architecture with floating-point arithmetic for high accuracy operations. In the IC and WCM units with fixed-point arithmetic, the proposed architecture uses an arrayed pipeline structure to shorten a circuit critical path delay. The implementation result shows that the proposed architecture reduces circuit area and power consumption by 11% and 15%, respectively.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2114/_p

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@ARTICLE{e96-a_11_2114,
author={Kosuke SHIMAZAKI, Shingo YOSHIZAWA, Yasuyuki HATAKAWA, Tomoko MATSUMOTO, Satoshi KONISHI, Yoshikazu MIYANAGA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing},
year={2013},
volume={E96-A},
number={11},
pages={2114-2119},
abstract={This paper presents a VLSI design of a Tomlinson-Harashima (TH) precoder for multi-user MIMO (MU-MIMO) systems. The TH precoder consists of LQ decomposition (LQD), interference cancellation (IC), and weight coefficient multiplication (WCM) units. The LQ decomposition unit is based on an application specific instruction-set processor (ASIP) architecture with floating-point arithmetic for high accuracy operations. In the IC and WCM units with fixed-point arithmetic, the proposed architecture uses an arrayed pipeline structure to shorten a circuit critical path delay. The implementation result shows that the proposed architecture reduces circuit area and power consumption by 11% and 15%, respectively.},
keywords={},
doi={10.1587/transfun.E96.A.2114},
ISSN={1745-1337},
month={November},}

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TY - JOUR
TI - A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2114
EP - 2119
AU - Kosuke SHIMAZAKI
AU - Shingo YOSHIZAWA
AU - Yasuyuki HATAKAWA
AU - Tomoko MATSUMOTO
AU - Satoshi KONISHI
AU - Yoshikazu MIYANAGA
PY - 2013
DO - 10.1587/transfun.E96.A.2114
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2013
AB - This paper presents a VLSI design of a Tomlinson-Harashima (TH) precoder for multi-user MIMO (MU-MIMO) systems. The TH precoder consists of LQ decomposition (LQD), interference cancellation (IC), and weight coefficient multiplication (WCM) units. The LQ decomposition unit is based on an application specific instruction-set processor (ASIP) architecture with floating-point arithmetic for high accuracy operations. In the IC and WCM units with fixed-point arithmetic, the proposed architecture uses an arrayed pipeline structure to shorten a circuit critical path delay. The implementation result shows that the proposed architecture reduces circuit area and power consumption by 11% and 15%, respectively.
ER -