We present a single-chip MPEG-4 audiovisual LSI in a 0.13 µm CMOS, 5-layer metal technology with 16 Mbit embedded DRAM, which integrates four 16 bit RISC and dedicated hardware accelerators including a 5 GOPS post filtering unit. It consumes 160 mW at 125 MHz and dissipates 80 nA in the standby mode. The chip is the world first LSI handling MPEG-4 CIF video encoding at 15 frames/sec and audio/speech encoding simultaneously.

The module-wise dynamic voltage and frequency scaling (MDVFS) scheme is applied to a single-chip H.264/MPEG-4 audio/visual codec LSI. The power consumption of the target module with controlled supply voltage and frequency is reduced by 40% in comparison with the operation without voltage or frequency scaling. The consumed power of the chip is 63 mW in decoding QVGA H.264 video at 15 fps and MPEG-4 AAC LC audio simultaneously. This LSI keep operating continuously even during the voltage transition of the target module by introducing the newly developed dynamic de-skewing system (DDS) which watches and control the clock edge of the target module.