In this paper we introduce a statistical quality model for delay testing that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that predicts the chip defect level that cause delay failure, including marginal small delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.

This paper presents a test generation method for sequential circuits under IDDQ testing environment and the identification of untestable faults based on the information of illegal states. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By using the two techniques together, high fault coverage and short computational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.