Test Generation for Sequential Circuits under IDDQ Testing

Toshiyuki MAEDA; Yoshinobu HIGAMI; Kozo KINOSHITA

Test Generation for Sequential Circuits under IDDQ Testing

Toshiyuki MAEDA, Yoshinobu HIGAMI, Kozo KINOSHITA

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This paper presents a test generation method for sequential circuits under IDDQ testing environment and the identification of untestable faults based on the information of illegal states. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By using the two techniques together, high fault coverage and short computational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.

Publication: IEICE TRANSACTIONS on Information Vol.E81-D No.7 pp.689-696

Publication Date: 1998/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)

Category: IDDQ Testing

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Toshiyuki MAEDA, Yoshinobu HIGAMI, Kozo KINOSHITA, "Test Generation for Sequential Circuits under IDDQ Testing" in IEICE TRANSACTIONS on Information, vol. E81-D, no. 7, pp. 689-696, July 1998, doi: .
Abstract: This paper presents a test generation method for sequential circuits under IDDQ testing environment and the identification of untestable faults based on the information of illegal states. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By using the two techniques together, high fault coverage and short computational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.
URL: https://globals.ieice.org/en_transactions/information/10.1587/e81-d_7_689/_p

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@ARTICLE{e81-d_7_689,
author={Toshiyuki MAEDA, Yoshinobu HIGAMI, Kozo KINOSHITA, },
journal={IEICE TRANSACTIONS on Information},
title={Test Generation for Sequential Circuits under IDDQ Testing},
year={1998},
volume={E81-D},
number={7},
pages={689-696},
abstract={This paper presents a test generation method for sequential circuits under IDDQ testing environment and the identification of untestable faults based on the information of illegal states. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By using the two techniques together, high fault coverage and short computational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - Test Generation for Sequential Circuits under IDDQ Testing
T2 - IEICE TRANSACTIONS on Information
SP - 689
EP - 696
AU - Toshiyuki MAEDA
AU - Yoshinobu HIGAMI
AU - Kozo KINOSHITA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E81-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 1998
AB - This paper presents a test generation method for sequential circuits under IDDQ testing environment and the identification of untestable faults based on the information of illegal states. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By using the two techniques together, high fault coverage and short computational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.
ER -