The post-annealing process has been investigated for (Ba, Sr)TiO3 [BST] thin films employed as a capacitor dielectric in 1 Gbit dynamic random access memories (DRAMs). The effects of post-annealing on morphology, crystallinity, and dielectric properties were examined for thin film capacitors with BST prepared on Pt electrodes by liquid source chemical vapor deposition (CVD). The direct annealing of BST capacitors caused a roughening in surface morphology of the upper Pt electrodes and BST films. However, the post-annealing of capacitors with a silicon dioxide passivation layer was found to cause little change in surface morphology of Pt and BST, and also no significant deterioration in leakage current. The improvement in crystallinity of BST films through post-annealing was confirmed at a temperature in the range 700-850 by X-ray diffraction (XRD) and transmission electron microscope (TEM). Moreover, the post-annealing experiments for BST films with different compositions showed that the post-annealing greatly increases the dielectric constant of BST films having approximately stoichiometric composition. The leakage and breakdown properties of BST films were also examined, indicating that excess Ti ions result in an increase of the turn-on voltage and the breakdown time. Based on these investigations, the electrical properties of dielectric constant ε 260, equivalent silicon dioxide thickness teq 0. 44 nm, and leakage current JL110-7 A/cm2 at 1. 9 V were successfully obtained for stoichiometric 30-nm-thick BST films post-annealed at 750. Hence, it can be concluded that the post-annealing is a promising technique to enhance the applicability of CVD-deposited BST films with conformal coverage to memory cell capacitors of 1 Gbit DRAMs.

Optical I/O core based on silicon photonics technology and optical/electrical assembly was developed as a fingertip-size optical module with high bandwidth density, low power consumption, and high temperature operation. The advantages of the optical I/O core, including hybrid integration of quantum dot laser diode and optical pin, allow us to achieve 300-m transmission at 25Gbps per channel when optical I/O core is mounted around field-programmable gate array without clock data recovery.

One of the most serious challenges facing the exponential performance growth in the information industry is a bandwidth bottleneck in inter-chip interconnects. We therefore propose a photonics-electronics convergence system with a silicon optical interposer. We examined integration between photonics and electronics and integration between light sources and silicon substrates, and we fabricated a conceptual model of the proposed system based on the results of those examinations. We also investigated the configurations and characteristics of optical components for the silicon optical interposer: silicon optical waveguides, silicon optical splitters, silicon optical modulators, germanium photodetectors, arrayed laser diodes, and spot-size converters. We then demonstrated the feasibility of the system by fabricating a high-density optical interposer by using silicon photonics integrated with these optical components on a single silicon substrate. As a result, we achieved error-free data transmission at 12.5 Gbps and a high bandwidth density of 6.6 Tbps/cm2 with the optical interposer. We think that this technology will solve the bandwidth bottleneck problem.

Thin (Ba0.75Sr0.25)TiO3 (BST) films to be used as dielectric materials in 256 Mbit DRAM capacitors were investigated. These films were deposited by an rf-sputtering method at substrate temperatures of 480 to 750. As substrate temperature increases, the dielectric constant to the films also increases, from 230 to 550. BST films prepared at temperatures higher than 700 show larger current leaks than films prepared at lower temperatures. A dielectric constant of 250, corresponding to a silicon oxide equivalent thickness (teq) of 0.47 nm, and a leak current density about 110-8 A/cm2 were obtained in 30-nm-thick film deposited at 660. Both of these values are sufficient for use in a 256 Mbit DRAM capacitor.