A LNA, an RF front-end and a 6th–order complex BPF for reconfigurable low-IF receivers are demonstrated in this work. Due to the noise cancellation, the two-stage LNA presents a low NF of 2.8 to 3.3 dB from 0.8 to 6 GHz. Moreover, the LNA delivers two kinds of gain curves with IIP3 of -2.6 dBm by employing the capacitive degeneration and the resistive gain-curve shaping in the second stage. The flicker noise corner frequency of the down-converter has been considered and the measured fC of the RF front-end is 200 kHz. The RF front-end also provides two kinds of gain curves. For the low-frequency mode, the conversion gain is 28.831.1 dB from 800 MHz to 2.4 GHz. For the high-frequency mode, the conversion gain is 26.827.4 dB from 3 to 5 GHz. The complex BPF is realized with gm-C LPFs by shifting the low-pass frequency response. With variable transconductances and capacitors, a fixed ratio of the centre frequency to the bandwidth (2) is achieved by varying the bandwidth and the centre frequency of the LPF simultaneously. The complex BPF has a variable bandwidth from 200 kHz to 6.4 MHz while achieving an image rejection of 44 dB.

In this paper, genetic algorithms is employed to determine the shape of a conducting cylinder buried in a half-space. Assume that a conducting cylinder of unknown shape is buried in one half-space and scatters the field incident from another half-space where the scattered filed is measured. Based on the boundary condition and the measured scattered field, a set of nonlinear integral equations is derived and the imaging problem is reformulated into an optimization problem. The genetic algorithm is then employed to find out the nearly global extreme solution of the object function such that the shape of the conducting scatterer can be suitably reconstructed. In our study, even when the initial guess is far away from the exact one, the genetic algorithm can avoid the local extremes and converge to a reasonably good solution. In such cases, the gradient-based methods often get stuck in local extremes. Numerical results are presented and good reconstruction is obtained both with and without the additive Gaussian noise.

Two-dimensional discrete wavelet transform (DWT) for processing image is conventionally designed by line-based architectures, which are simple and have low complexity. However, they suffer from two main shortcomings - the memory required for storing intermediate data and the long latency of computing wavelet coefficients. This work presents a new block-based architecture for computing lifting-based 2-D DWT coefficients. This architecture yields a significantly lower buffer size. Additionally, the latency is reduced from N2 down to 3N as compared to the line-based architectures. The proposed architecture supports the JPEG2000 default filters and has been realized in ARM-based ALTERA EPXA10 Development Board at a frequency of 44.33 MHz.

Novel low phase noise quadrature voltage-controlled oscillator (QVCO) and quadrature injection locked frequency divider (QILFD) with two coupled Hartley VCOs are proposed and implemented using the standard TSMC 0.18 µm CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.7 V supply voltage, the output phase noise of the QVCO is -124 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 4.12 GHz, and the figure of merit is -185 dBc/Hz. At the supply voltage of 1.7 V, the total power consumption is 13.1 mW. At the supply voltage of 1.5 V, the tuning range of the free-running QILFD is from 2.05 GHz to 2.36 GHz, about 310 MHz, and the locking range of the ILFD is from 3.99 to 5.19 GHz, about 1.20 GHz, at the injection signal power of 0 dBm.

This paper proposes a wide-locking range divide-by-3 frequency divider employing 3D helical inductors fabricated in the 0.18-µm 1P6M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size. At the supply voltage of 1.2 V, the divider free-running frequency is tunable from 2.1 GHz to 2.6 GHz, and at the incident power of 0 dBm the locking range is about 2.11 GHz (29.16%), from the incident frequency 5.99 GHz to 8.1 GHz. The core power consumption is 4.56 mW. The die area is 0.6640.831 mm2.

A dual-band divide-by-2 quadrature injection-locked frequency divider (QILFD) is proposed to achieve high-speed, low power, wide-locking range, and accurate quadrature output phases. The QILFD consists of two dual-resonance differential voltage controlled oscillators and four coupling NMOS injectors in a ring configuration. The injectors are used as coupling devices of two differential ILFDs and are also used as common source amplifiers. The proposed QILFD has been implemented with the TSMC 90 nm CMOS technology and the core power consumption is 2.31 mW at the dc drain-source bias of 0.5 V. At the input power of 0 dBm, the low-band and high-band divide-by-2 operation ranges are respectively from 7.0 GHz to 10.1 GHz and 19.8 GHz to 24.6 GHz.

Network Functional Virtualization (NFV) is a high-performance network interconnection technology that allows access to traditional network transport devices through virtual network links. It is widely used in cloud computing and other high-concurrent access environments. However, there is a long delay in the introduction of software NFV solutions. Other hardware I/O virtualization solutions don't scale very well. Therefore, this paper proposes a virtualization implementation method on 100Gbps high-speed Field Programmable Gate Array (FPGA) network accelerator card, which uses FPGA accelerator to improve the performance of virtual network devices. This method uses the single root I/O virtualization (SR-IOV) technology to allow 256 virtual links to be created for a single Peripheral Component Interconnect express (PCIe) device. And it supports data transfer with virtual machine (VM) in the way of Peripheral Component Interconnect (PCI) passthrough. In addition, the design also adopts the shared extensible queue management mechanism, which supports the flexible allocation of more than 10,000 queues on virtual machines, and ensures the good isolation performance in the data path and control path. The design provides high-bandwidth transmission performance of more than 90Gbps for the entire network system, meeting the performance requirements of hyperscale cloud computing clusters.

Researchers have developed several social-based routing protocols for delay tolerant networks (DTNs) over the past few years. Two main routing metrics to support social-based routing in DTNs are centrality and similarity metrics. These two metrics help packets decide how to travel through the network to achieve short delay or low drop rate. This study presents a new routing scheme called Community-Relevance based Opportunistic routing (CROP). CROP uses a different message forwarding approach in DTNs by combining community structure with a new centrality metric called community relevance. One fundamental change in this approach is that community relevance values do not represent the importance of communities themselves. Instead, they are computed for each community-community relationship individually, which means that the level of importance of one community depends on the packet's destination community. The study also compares CROP with other routing algorithms such as BubbleRap and SimBet. Simulation results show that CROP achieves an average delivery ratio improvement of at least 30% and can distribute packets more fairly within the network.

A novel divide-by-3 injection-locked frequency divider (ILFD) is proposed. The ILFD circuit is realized with a cross-coupled n-core MOS LC-tank oscillator embedded with a push-push signal generator and two injection MOSFETs for coupling the injection signal into the resonator. The ILFD uses the linear mixer to extend the locking range and has been implemented in a standard 0.18 µm CMOS process. The core power consumption of the ILFD core is 3.12 mW. The divider's free-running frequency is tunable from 4.26 GHz to 4.9 GHz by tuning the varactor's control bias, and at the incident power of 0 dBm the locking range of the ILFD used as a divide-by-3 divider is 1.5 GHz, from 12.5 GHz to 14.0 GHz.

The genetic algorithm is used to reconstruct the shapes of multiple perfectly conducting cylinders. Based on the boundary condition and the measured scattered field, a set of nonlinear integral equations is derived and the imaging problem is reformulated into an optimization problem. The genetic algorithm is then employed to find out the global extreme solution of the object function. Numerical examples are given to demonstrate the capability of the inverse algorithm. Good reconstruction is obtained even when the multiple scattering between two conductors is serious. In addition, the effect of Gaussian noise on the reconstruction results is investigated.