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[Author] Yasuhide MACHIDA(1hit)
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On-Chip Testing for 30 K-Gate Masterslice
Shinji SATO Hiromasa TAKAHASHI Yasuhide MACHIDA Gensuke GOTO
- LETTER-Silicon Devices and Integrated Circuits
- Vol:
- E69-E No:4
- Page(s):
- 267-269
On-chip testing for 30 K-gate masterslice with freely configured SRAM AND/OR ROM blocks was investigated. Multiplier fault coverage was about 93 percent. The validity of on-chip testing was confirmed in masterslices containing over 20 K gates with memory blocks.
