On-Chip Testing for 30 K-Gate Masterslice

Shinji SATO; Hiromasa TAKAHASHI; Yasuhide MACHIDA; Gensuke GOTO

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Shinji SATO, Hiromasa TAKAHASHI, Yasuhide MACHIDA, Gensuke GOTO, "On-Chip Testing for 30 K-Gate Masterslice" in IEICE TRANSACTIONS on transactions, vol. E69-E, no. 4, pp. 267-269, April 1986, doi: .
Abstract: On-chip testing for 30 K-gate masterslice with freely configured SRAM AND/OR ROM blocks was investigated. Multiplier fault coverage was about 93 percent. The validity of on-chip testing was confirmed in masterslices containing over 20 K gates with memory blocks.
URL: https://globals.ieice.org/en_transactions/transactions/10.1587/e69-e_4_267/_p

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@ARTICLE{e69-e_4_267,
author={Shinji SATO, Hiromasa TAKAHASHI, Yasuhide MACHIDA, Gensuke GOTO, },
journal={IEICE TRANSACTIONS on transactions},
title={On-Chip Testing for 30 K-Gate Masterslice},
year={1986},
volume={E69-E},
number={4},
pages={267-269},
abstract={On-chip testing for 30 K-gate masterslice with freely configured SRAM AND/OR ROM blocks was investigated. Multiplier fault coverage was about 93 percent. The validity of on-chip testing was confirmed in masterslices containing over 20 K gates with memory blocks.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - On-Chip Testing for 30 K-Gate Masterslice
T2 - IEICE TRANSACTIONS on transactions
SP - 267
EP - 269
AU - Shinji SATO
AU - Hiromasa TAKAHASHI
AU - Yasuhide MACHIDA
AU - Gensuke GOTO
PY - 1986
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E69-E
IS - 4
JA - IEICE TRANSACTIONS on transactions
Y1 - April 1986
AB - On-chip testing for 30 K-gate masterslice with freely configured SRAM AND/OR ROM blocks was investigated. Multiplier fault coverage was about 93 percent. The validity of on-chip testing was confirmed in masterslices containing over 20 K gates with memory blocks.
ER -