This paper presents the implementation of a 31-tap FIR Hilbert transform digital filter chip used in the digital-IF receivers, to confirm the effectiveness of our new design method. Our design method that we previously reported is based on a computation sharing multiplier using a new horizontal and vertical common subexpression techniques. A 31-tap FIR Hilbert transform digital filter was implemented and fabricated in 0.35 µm CMOS standard cell library. The chip's core contains approximately 33k transistors and occupies 0.86 mm2. The chip also has an operating speed of 70 MHz over. The implementation results show that the proposed Hilbert transformer has a smallest cost factor and so that is a high performance filter.

An adiabatic logic is a technique to design low power digital VLSI's. This paper describes the design and VLSI implementation of a multiplier using a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance have been evaluated using a 44-bit 2PADCL multiplier fabricated in a 1.2 µm CMOS process. The experimental results show that the multiplier was operated with clock frequencies 800 kHz. The total power dissipation of the 44-bit 2PADCL multiplier was also 5.19 mW at the 1.5 V DC power supply voltage.

Quantum circuits for elementary arithmetic operations are important not only for implementing Shor's factoring algorithm on a quantum computer but also for understanding the computational power of small quantum circuits, such as linear-size or logarithmic-depth quantum circuits. This paper surveys some recent approaches to constructing efficient quantum circuits for elementary arithmetic operations and their applications to Shor's factoring algorithm. It covers addition, comparison, and the quantum Fourier transform used for addition.

This paper describes a design of a Carry Propagation Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1 bit CPFA/S is compared with that of the CMOS 1 bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/3 as high as that of the CMOS circuits. The transistors count, propagation-delay time and energy dissipation of the ADCL 4 bit CPFA/S are compared with those of the ADCL 4 bit Ripple Carry Adder/Subtracter (RCA/S). The transistors count and propagation-delay time are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1 bit CPFA/S fabricated in a 1.2 µm CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1 MHz. In addition, the total power dissipation of the ADCL 1 bit CPFA/S is 28.7 µW including the power supply.