A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library

Yasuhiro TAKAHASHI; Toshikazu SEKINE; Michio YOKOYAMA

doi:10.1093/ietfec/e90-a.7.1376

A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library

Yasuhiro TAKAHASHI, Toshikazu SEKINE, Michio YOKOYAMA

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This paper presents the implementation of a 31-tap FIR Hilbert transform digital filter chip used in the digital-IF receivers, to confirm the effectiveness of our new design method. Our design method that we previously reported is based on a computation sharing multiplier using a new horizontal and vertical common subexpression techniques. A 31-tap FIR Hilbert transform digital filter was implemented and fabricated in 0.35 µm CMOS standard cell library. The chip's core contains approximately 33k transistors and occupies 0.86 mm². The chip also has an operating speed of 70 MHz over. The implementation results show that the proposed Hilbert transformer has a smallest cost factor and so that is a high performance filter.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.7 pp.1376-1383

Publication Date: 2007/07/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.7.1376

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Yasuhiro TAKAHASHI, Toshikazu SEKINE, Michio YOKOYAMA, "A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 7, pp. 1376-1383, July 2007, doi: 10.1093/ietfec/e90-a.7.1376.
Abstract: This paper presents the implementation of a 31-tap FIR Hilbert transform digital filter chip used in the digital-IF receivers, to confirm the effectiveness of our new design method. Our design method that we previously reported is based on a computation sharing multiplier using a new horizontal and vertical common subexpression techniques. A 31-tap FIR Hilbert transform digital filter was implemented and fabricated in 0.35 µm CMOS standard cell library. The chip's core contains approximately 33k transistors and occupies 0.86 mm². The chip also has an operating speed of 70 MHz over. The implementation results show that the proposed Hilbert transformer has a smallest cost factor and so that is a high performance filter.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.7.1376/_p

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@ARTICLE{e90-a_7_1376,
author={Yasuhiro TAKAHASHI, Toshikazu SEKINE, Michio YOKOYAMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library},
year={2007},
volume={E90-A},
number={7},
pages={1376-1383},
abstract={This paper presents the implementation of a 31-tap FIR Hilbert transform digital filter chip used in the digital-IF receivers, to confirm the effectiveness of our new design method. Our design method that we previously reported is based on a computation sharing multiplier using a new horizontal and vertical common subexpression techniques. A 31-tap FIR Hilbert transform digital filter was implemented and fabricated in 0.35 µm CMOS standard cell library. The chip's core contains approximately 33k transistors and occupies 0.86 mm². The chip also has an operating speed of 70 MHz over. The implementation results show that the proposed Hilbert transformer has a smallest cost factor and so that is a high performance filter.},
keywords={},
doi={10.1093/ietfec/e90-a.7.1376},
ISSN={1745-1337},
month={July},}

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TY - JOUR
TI - A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1376
EP - 1383
AU - Yasuhiro TAKAHASHI
AU - Toshikazu SEKINE
AU - Michio YOKOYAMA
PY - 2007
DO - 10.1093/ietfec/e90-a.7.1376
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2007
AB - This paper presents the implementation of a 31-tap FIR Hilbert transform digital filter chip used in the digital-IF receivers, to confirm the effectiveness of our new design method. Our design method that we previously reported is based on a computation sharing multiplier using a new horizontal and vertical common subexpression techniques. A 31-tap FIR Hilbert transform digital filter was implemented and fabricated in 0.35 µm CMOS standard cell library. The chip's core contains approximately 33k transistors and occupies 0.86 mm². The chip also has an operating speed of 70 MHz over. The implementation results show that the proposed Hilbert transformer has a smallest cost factor and so that is a high performance filter.
ER -