A three-dimensional simulation program of oblique rotating ion implantation using the Monte Carlo method has been newly developed to simulate the N- and N+ drain formation of the gate/N- overlapped LDD MOSFET's. The binary scattering approximation is used for nuclear scattering, and the Lindhard-Scharff formula and the Bethe-Bloch formula are used for electronic scattering. The azimuth of the ion is initialized by a random number uniformly distributed between 0 and 2π to express the wafer rotation. The topography of the MOSFET's is approximately expressed in algebraic form to obtain effectively the touchdown points of ion particles on the target surface. The vectorized Monte Carlo method is used to reduce the CPU time. The simulation provides the two-dimensional distribution of the dopant and the Frenkel pairs (vacancy-interstitial), using the Kinchin-Pease equation. From the results of the calculation, it appears that the overlap length, which is defined as the distance between the polysilicon gate edge and the intersection of the 104/cm (equi-concentration/doseline) on the silicon surface, increases in accordance with the increase of the incidence angle of the ion beam, and it extends to 0.1 µm when 40-keV of phosphorus is implanted with an incidence angle of 60. It also appears that the concentration of the Frenkel pairs becomes lower in accordance with an increase in the incidence angle of the ion beam. The simulation also reveals that the effect of a shadowed drain region caused by the polysilicon gate is enlarged in accordance with the increase in the incidence angle, especially in the case of an incidence angle of 60, when the shadowed N+ drain region extends to the point 0.6 µm from the edge of the sidewall which is 0.35 µm in height.

This paper describes state-of-the-art process and device technologies for 3-D ICs and the prospect of its possible applications. 3-dimensional monolithic multilayer structures are expected to be appropriate for high density CMOS and image processing devices. Memory cell and fundamental gate structures have been fabricated with stacked PMOS and NMOS layers. A functional model chip which integrates photosensors, A/D converterss and arithmetic logic units demonstrated a real time image processing capability based on the parallel signal processing. The 3-D structure essentially offers a lot of advantages over conventional ULSI structures, but innovative technology improvement in SOI (Silicon-on-Insulator) and refractive metal interconnection is necessary for realizing practically available 3-D chips.

We investigated the limit of applicability of the impact ionization model as a function of the local electric field by using of the Monte Carlo technique. We found out that the deviation between the Monte Carlo result and estimation of the model of the local electric field becomes significant where the field-gradient is high and for our electric field profile it is about 1.0 1010 V/cm2. We also calculated the substrate current by the regional Monte Carlo calculation. We proposed an absorbent boundary at the end of the calculation region to reduce the computational time. Computational time is greatly reduced and the result is the same as that calculated by the conventional boundary.