3-D IC Technologies and Possible Application

Yoichi AKASAKA

3-D IC Technologies and Possible Application

Yoichi AKASAKA

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This paper describes state-of-the-art process and device technologies for 3-D ICs and the prospect of its possible applications. 3-dimensional monolithic multilayer structures are expected to be appropriate for high density CMOS and image processing devices. Memory cell and fundamental gate structures have been fabricated with stacked PMOS and NMOS layers. A functional model chip which integrates photosensors, A/D converterss and arithmetic logic units demonstrated a real time image processing capability based on the parallel signal processing. The 3-D structure essentially offers a lot of advantages over conventional ULSI structures, but innovative technology improvement in SOI (Silicon-on-Insulator) and refractive metal interconnection is necessary for realizing practically available 3-D chips.

Publication: IEICE TRANSACTIONS on Electronics Vol.E74-C No.2 pp.325-336

Publication Date: 1991/02/25

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Type of Manuscript: INVITED PAPER

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Yoichi AKASAKA

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Yoichi AKASAKA, "3-D IC Technologies and Possible Application" in IEICE TRANSACTIONS on Electronics, vol. E74-C, no. 2, pp. 325-336, February 1991, doi: .
Abstract: This paper describes state-of-the-art process and device technologies for 3-D ICs and the prospect of its possible applications. 3-dimensional monolithic multilayer structures are expected to be appropriate for high density CMOS and image processing devices. Memory cell and fundamental gate structures have been fabricated with stacked PMOS and NMOS layers. A functional model chip which integrates photosensors, A/D converterss and arithmetic logic units demonstrated a real time image processing capability based on the parallel signal processing. The 3-D structure essentially offers a lot of advantages over conventional ULSI structures, but innovative technology improvement in SOI (Silicon-on-Insulator) and refractive metal interconnection is necessary for realizing practically available 3-D chips.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e74-c_2_325/_p

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@ARTICLE{e74-c_2_325,
author={Yoichi AKASAKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={3-D IC Technologies and Possible Application},
year={1991},
volume={E74-C},
number={2},
pages={325-336},
abstract={This paper describes state-of-the-art process and device technologies for 3-D ICs and the prospect of its possible applications. 3-dimensional monolithic multilayer structures are expected to be appropriate for high density CMOS and image processing devices. Memory cell and fundamental gate structures have been fabricated with stacked PMOS and NMOS layers. A functional model chip which integrates photosensors, A/D converterss and arithmetic logic units demonstrated a real time image processing capability based on the parallel signal processing. The 3-D structure essentially offers a lot of advantages over conventional ULSI structures, but innovative technology improvement in SOI (Silicon-on-Insulator) and refractive metal interconnection is necessary for realizing practically available 3-D chips.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - 3-D IC Technologies and Possible Application
T2 - IEICE TRANSACTIONS on Electronics
SP - 325
EP - 336
AU - Yoichi AKASAKA
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 1991
AB - This paper describes state-of-the-art process and device technologies for 3-D ICs and the prospect of its possible applications. 3-dimensional monolithic multilayer structures are expected to be appropriate for high density CMOS and image processing devices. Memory cell and fundamental gate structures have been fabricated with stacked PMOS and NMOS layers. A functional model chip which integrates photosensors, A/D converterss and arithmetic logic units demonstrated a real time image processing capability based on the parallel signal processing. The 3-D structure essentially offers a lot of advantages over conventional ULSI structures, but innovative technology improvement in SOI (Silicon-on-Insulator) and refractive metal interconnection is necessary for realizing practically available 3-D chips.
ER -