In this work, a statistical analysis is performed for a simple constrained high-order Yule-Walker (YW) tone frequency estimator obtained from the first equation of the constrained high-order YW equations. Explicit expressions for its estimation bias and variance are efficiently derived by virtue of a Taylor series expansion technique. Especially, being explicit in terms of frequency, data length and Signal-to-Noise Ratio (SNR) value, the resulting bias expression can not be obtained by using the asymptotic analyses used for the parameter estimation methods. The obtained expressions are compared with their counterparts of the Pisarenko tone frequency estimator. Simulations are performed to support the theoretical results.

A scheme for a low-voltage CMOS syllabic-companding log domain filter with wide dynamic range is proposed and its prototype is presented. A nodal voltage which is fixed in a conventional filter based on the dynamically adjustable biasing (DAB) technique is adapted for change of input envelope to achieve wide dynamic range. Externally linear and time invariant (ELTI) relation between an input and an output is guaranteed by a state variable correction (SVC) circuit which is also proposed for low-voltage operation. To demonstrate the proposed scheme, a fifth-order Chebychev low-pass filter with 100-kHz cutoff frequency is designed and fabricated in a standard 0.35-µm CMOS process. The filter has a 78-dB dynamic range and consumes 200-µW power from a 0.8-V power supply.

In this paper, the Pisarenko and the Constrained Yule-Walker (CYW) estimators of a tone frequency are first newly derived from the viewpoint of using directly the autocorrelation coefficients. Then, simulation of these two estimators is carried out in some detail. The simulation results show that compared with the Pisarenko estimator the CYW estimator, which has not been adequately studied, works poorly for low and moderate Signal-to-Noise Ratio (SNR) values. However, in case of high SNR value, it yields very small bias and comparable estimation variance, and thus produces more accurate tone frequency estimates.

Adaptive estimation of nonstationary sinusoidal signals or quasi-periodic signals in additive noise is of essential importance in many diverse engineering fields, such as communications, biomedical engineering, power systems, pitch detection in transcription and so forth. So far, Kalman filtering based techniques, recursive least square (RLS), simplified RLS (SRLS) and LMS algorithms, for examples, have been developed for this purpose. This work presents in detail a performance analysis for the SRLS algorithm proposed recently in the literature, which is used to estimate an enhanced sinusoid. Its dynamic and tracking properties, noise and lag misadjustments are developed and discussed. It is found that the SRLS estimator is biased, and its misadjustments are functions of not only the noise variance but also, unpleasantly, of the signal parameters. Simulations demonstrate the validity of the analysis. Application of the SRLS to a real-life piano sound is also given to peek at its effectiveness.

This paper proposes a synthesis method of all low-voltage CMOS instantaneous-companding log domain integrators. The method is based on the exhaustive search of all low-voltage CMOS instantaneous-companding log domain integrators. All the integrators are derived from a general block diagram. A function of each block can be realized by any of a family of circuits and elemental circuits chosen from such families are combined to build an integrator. It is clarified that each family contains a few circuit topologies. All topologies of integrators including new ones are obtained from combinational procedure. Comparing characteristics of all generated integrators, ones satisfying required performances are found out.

This paper presents a novel method of an on-sensor motion vector estimation. One of the key techniques is an iterative block matching algorithm using high-speed interpolated pictures. This technique allows us to estimate the video-rate (30 frame/s) motion vectors accurately from the motion vectors obtained at high-speed frames. The proposed iterative block matching reduces the computational complexity by a factor of more than one tenth compared to the conventional full search block matching algorithm. This property is particularly useful for the reduction of the power dissipation of video encoder. Another proposed technique is a high-speed non-destructive image sensing. This technique is essential to obtain high-speed interpolated pictures while maintaining high image quality in video-rate image sensing. The estimated power dissipation of the designed CMOS image sensor is sufficiently low, allowing us to achieve a totally low-power design of one-chip CMOS cameras integrating an image sensor and a video encoder.

This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.

This paper presents an analog 2-dimensional discrete cosine transform (2-D DCT) processor for focal-plane image compression. The on-chip analog 2-D DCT processor can process directly the analog signal of the CMOS image sensor. The analog-to-digital conversion (ADC) is preformed after the 2-D DCT, and this leads to efficient AD conversion of video signals. Most of the 2-D DCT coefficients can be digitized by a relatively low-resolution ADC or a zero detector. The quantization process after the 2-D DCT can be realized by the ADC at the same time. The 88-point analog 2-D DCT processor is designed by switched-capacitor (SC) coefficient multipliers and an SC analog memory based on 0.35µm CMOS technology. The 2-D DCT processor has sufficient precision, high processing speed, low power dissipation, and small silicon area. The resulting smart image sensor chips with data compression and digital transmission functions are useful for the high-speed image acquisition devices and portable digital video camera systems.

Band connections employed in active cancellation circuits for effective reduction of digital substrate noise are proposed. An almost-odd-symmetrical noise characteristic is utilized for canceling out noises. Advancing this idea, interlaced connections of four bands are also proposed. Excess cancellation by those bands is more effective for noise reduction in a guard ring than a cancellation by two bands. Use of L-shaped bands on the basis of the interlaced connection suppresses the noise more. Simulation and experimental results show that the proposed band connections reduce the noise.

This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.

This paper presents a low-power video A/D conversion technique using features of moving pictures. Neighboring frames in typical video sequences and neighboring pixels in each video frame are highly correlated. This property is effectively used for the video A/D conversion to reduce the number of comparators and the resulting power consumption. A set of reference voltages is given to a comparator array so that the iterative A/D conversion converges in the logarithmic order of the prediction error. Simulation results using standard moving pictures showed that the average number of iterations for the A/D conversion is less than 3 for all the moving pictures tested. In the proposed 12 b A/D converter, the number of comparators can be reduced to about 1/5 compared with that of the two-step flash A/D converters, which are commonly used for video applications. The A/D converter is particularly useful for the integration to CMOS image sensors.