NAND-structured trench capacitor cell technologies for 256 Mb DRAM and beyond have been developed. The NAND-structured cell has four memory cells connected in series. The cell size can be reduced to 56% of the conventional cell. A substrate plate trench capacitor cell was adapted to this layout. The NAND-structured trench capacitor cell can achieve sufficient storage capacitance within the restricted capacitor area. A sufficient capacitance of 40 fF was achieved when the size and depth of trench were 0.5 µm and 5.0 µm, respectively. The most important point for realizing the NAND-structured trench capacitor cell is how to reduce the leakage current from the storage node. There are two main sources; one is the leakage current to the neighboring cells, the other is the leakage current to Pwell. These leakage currents have been investigated. An experimental 256 Mb DRAM with the NAND-structured cell was fabricated using the 0.4 µm design rule. The chip size is 464 mm2, which is 68% of a conventional DRAM of the same design rule. This is the result of the reduction of the memory cell area by the NAND-structured cell and the introduction of the open-bit-line arrangement.